JAJS472C August   2010  – April 2018 TPS54320

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と負荷電流との関係
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Continuous Current Mode Operation (CCM)
      3. 7.3.3  VIN and Power VIN Pins (VIN and PVIN)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Adjusting the Output Voltage
      6. 7.3.6  Safe Start-up into Prebiased Outputs
      7. 7.3.7  Error Amplifier
      8. 7.3.8  Slope Compensation
      9. 7.3.9  Enable and Adjusting UVLO
      10. 7.3.10 Slow Start (SS/TR)
      11. 7.3.11 Power Good (PWRGD)
      12. 7.3.12 Bootstrap Voltage (BOOT) and Low Dropout Operation
      13. 7.3.13 Sequencing (SS/TR)
      14. 7.3.14 Output Overvoltage Protection (OVP)
      15. 7.3.15 Overcurrent Protection
        1. 7.3.15.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.15.2 Low-Side MOSFET Overcurrent Protection
      16. 7.3.16 Thermal Shutdown
      17. 7.3.17 Small Signal Model for Loop Response
      18. 7.3.18 Simple Small Signal Model for Peak Current Mode Control
      19. 7.3.19 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Adjustable Switching Frequency and Synchronization (RT/CLK)
      2. 7.4.2 Adjustable Switching Frequency (RT Mode)
      3. 7.4.3 Synchronization (CLK Mode)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Operating Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Slow-Start Capacitor Selection
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  UVLO Set Point
        9. 8.2.2.9  Output Voltage Feedback Resistor Selection
          1. 8.2.2.9.1 Minimum Output Voltage
        10. 8.2.2.10 Compensation Component Selection
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントのサポート
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Sequencing (SS/TR)

Many of the common power-supply sequencing methods can be implemented using the SS/TR, EN, and PWRGD pins.

Figure 20 shows the sequential method using two TPS54320 devices. The power good of the first device is coupled to the EN pin of the second device which enables the second power supply once the primary supply reaches regulation. Figure 21 shows the results of Figure 20.

TPS54320 startup_lvs982.gifFigure 20. Sequential Start-Up Sequence
SPACE
TPS54320 seq_stup_lvs981.gif
Figure 21. Sequential Start-Up Using EN and PWRGD

Figure 22 shows the method implementing ratiometric sequencing by connecting the SS/TR pins of two devices together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow-start time, the pullup current source must be doubled in Equation 4. Figure 23 shows the results of Figure 22.

TPS54320 ratio_stup_lvs982.gifFigure 22. Ratiometric Start-Up Sequence
SPACE
TPS54320 simul_stup_lvs981.gif
Figure 23. Ratiometric Start-Up Using Coupled SS/TR Pins

Ratiometric and simultaneous power-supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 24 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 5 and Equation 6, the tracking resistors can be calculated to initiate the Vout2 slightly before, after, or at the same time as Vout1. Equation 7 is the voltage difference between Vout1 and Vout2.

To design a ratiometric start-up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 5 and Equation 6 for ΔV. Equation 7 results in a positive number for applications where the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. Figure 25 and Figure 26 show the results for positive ΔV and negative ΔV respectively.

The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset, 29 mV) in the slow-start circuit and the offset created by the pullup current source (Iss, 2.3 μA) and tracking resistors, the Vssoffset and Iss are included as variables in the equations. Figure 27 shows the result when ΔV = 0 V.

To ensure proper operation of the device, the calculated R1 value from Equation 5 must be greater than the value calculated in Equation 8.

Equation 5. TPS54320 eq5_r1_lvs949.gif
Equation 6. TPS54320 eq6_r2_lvs949.gif
Equation 7. TPS54320 eq7_dv_lvs949.gif
Equation 8. TPS54320 eq_deltav_lvs949.gif
TPS54320 ratiosimul_stup_lvs982.gifFigure 24. Ratiometric and Simultaneous Start-Up Sequence
TPS54320 ratio_vout1_lvs981.gif
Figure 25. Ratiometric Start-Up With Vout1 Leading Vout2
TPS54320 ratio_vout2_lvs981.gif
Figure 26. Ratiometric Start-Up With Vout2 Leading Vout1
TPS54320 ratio_sstr_lvs981.gif
Figure 27. Simultaneous Start-Up