JAJS472C August   2010  – April 2018 TPS54320

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と負荷電流との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Continuous Current Mode Operation (CCM)
      3. 7.3.3  VIN and Power VIN Pins (VIN and PVIN)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Adjusting the Output Voltage
      6. 7.3.6  Safe Start-up into Prebiased Outputs
      7. 7.3.7  Error Amplifier
      8. 7.3.8  Slope Compensation
      9. 7.3.9  Enable and Adjusting UVLO
      10. 7.3.10 Slow Start (SS/TR)
      11. 7.3.11 Power Good (PWRGD)
      12. 7.3.12 Bootstrap Voltage (BOOT) and Low Dropout Operation
      13. 7.3.13 Sequencing (SS/TR)
      14. 7.3.14 Output Overvoltage Protection (OVP)
      15. 7.3.15 Overcurrent Protection
        1. 7.3.15.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.15.2 Low-Side MOSFET Overcurrent Protection
      16. 7.3.16 Thermal Shutdown
      17. 7.3.17 Small Signal Model for Loop Response
      18. 7.3.18 Simple Small Signal Model for Peak Current Mode Control
      19. 7.3.19 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Adjustable Switching Frequency and Synchronization (RT/CLK)
      2. 7.4.2 Adjustable Switching Frequency (RT Mode)
      3. 7.4.3 Synchronization (CLK Mode)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Operating Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Slow-Start Capacitor Selection
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  UVLO Set Point
        9. 8.2.2.9  Output Voltage Feedback Resistor Selection
          1. 8.2.2.9.1 Minimum Output Voltage
        10. 8.2.2.10 Compensation Component Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントのサポート
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.10 Compensation Component Selection

There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60° and 90°. The method presented here ignores the effects of the slope compensation that is internal to the TPS54320. Since the slope compensation is ignored, the actual crossover frequency is usually lower than the crossover frequency used in the calculations. Use SwitcherPro software for a more accurate design.

Type III compensation is used to achieve a high-bandwidth, high-phase margin design. This design targets a crossover frequency (bandwidth) of 48 kHz (1/10 of the switching frequency). Using Equation 32 and Equation 33, the power stage pole and zero are calculated at 6.46 and 1778 kHz, respectively. For the output capacitance, CO, use a derated value of 22.4 µF.

Equation 32. TPS54320 eq31_fpmod_lvs982.gif
Equation 33. TPS54320 eq32_fzmod_lvs982.gif

Now the compensation components can be calculated. First, calculate the value for R4 which sets the gain of the compensated network at the crossover frequency. Use Equation 34 to determine the value of R4.

Equation 34. TPS54320 eq33_r4_lvs982.gif

Next calculate the value of C4. Together with R4, C4 places a compensation zero at the modulator pole frequency. Use Equation 35 to determine the value of C4.

Equation 35. TPS54320 eq34_c4_lvs982.gif

Using Equation 34 and Equation 35, the standard values for R4 and C4 are 1.78 kΩ and 0.015 µF. The next higher standard value for C4 is selected to give a compensation zero that is slightly lower in frequency than the power stage pole.

To provide a zero around the crossover frequency to boost the phase at crossover, a capacitor (C11) is added parallel to R8. The value of this capacitor is given by Equation 36. The nearest standard value for C11 is 100 pF.

Equation 36. TPS54320 eq35_c11_lvs982.gif

Use of the feed-forward capacitor, C11, creates a low-AC impedance path from the output voltage to the VSENSE input of the IC that can couple noise at the switching frequency into the control loop. TI does not recommend use of a feed-forward capacitor for high-output voltage ripple designs (greater than 15-mV peak to peak at the VSENSE input) operating at duty cycles of less than 30%. When using the feed-forward capacitor, C11, always limit the closed loop bandwidth to no more than 1/10 of the switching frequency, ƒsw.

An additional high-frequency pole can be used if necessary by adding a capacitor in parallel with the series combination of R4 and C4. Equation 37 gives the pole frequency. This pole is set at roughly half of the switching frequency (of 480 kHz) by use of a 330-pF capacitor for C6. This helps attenuate any high-frequency signals that might couple into the control loop.

Equation 37. TPS54320 eq36_fp_lvs982.gif