JAJS371 データシート

JAJS371D January 2009 – September 2023 TPS54332

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

DDA|8
- MPDS092F

サーマルパッド・メカニカル・データ

DDA|8
- PPTD087E

発注情報

8.2.2.8 Compensation Components

The external compensation used with the TPS54332 allows for a wide range of output filter configurations. A large range of capacitor values and types of dielectric are supported. The design example uses ceramic X5R dielectric output capacitors, but other types are supported.

TI recommends a type II compensation scheme for the TPS54332. The compensation components are chosen to set the desired closed-loop crossover frequency and phase margin for output filter components. The type II compensation has the following characteristics; a DC gain component, a low-frequency pole, and a mid-frequency zero or pole pair.

The DC gain is determined by Equation 16.

Equation 16.

G_{D C} = \frac{V_{G G M} \times V_{R E F}}{V_{O}}

Where:

V_GGM = 800
V_REF = 0.8 V

The low-frequency pole is determined by Equation 17.

Equation 17.

F_{P O} = \frac{1}{2 \times π \times R_{O O} \times C_{Z}}

R_OA = 8.696 MΩ.

The mid-frequency zero is determined by Equation 18.

Equation 18.

F_{Z 1} = \frac{1}{2 \times π \times R_{Z} \times C_{Z}}

And, the mid-frequency pole is given by Equation 19.

Equation 19.

F_{P 1} = \frac{1}{2 \times π \times R_{Z} \times C_{P}}

The first step is to choose the closed-loop crossover frequency. The closed-loop crossover frequency must be less than 1/8 of the minimum operating frequency, but for the TPS54332 TI recommends that the maximum closed-loop crossover frequency be not greater than 75 kHz. Next, the required gain and phase boost of the crossover network must be calculated. By definition, the gain of the compensation network must be the inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is much higher than the closed-loop crossover frequency, the gain of the modulator and output filter can be approximated by Equation 20.

Equation 20.

G a i n = - 20 \times l o g (2 \times π \times R_{S E N S E} \times F_{C O} \times C_{O})

Where:

R_SENSE = 1 Ω / 12

F_CO = Closed-loop crossover frequency

C_O = Output capacitance

The phase loss is given by Equation 21.

Equation 21.

P L = α \times t a n (2 \times π \times F_{C O} \times R_{E S R} \times C_{O}) - α \times t a n (2 \times π \times F_{C O} \times R_{O} \times C_{O}) - 10 d B

Where:

R_ESR = Equivalent series resistance of the output capacitor

R_O = V_O/I_O

The measured overall loop response for the circuit is given in Figure 8-9. Note that the actual closed-loop crossover frequency is higher than intended at about 25 kHz. This is primarily due to variation in the actual values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall the design has greater than 60 degrees of phase margin and is completely stable over all combinations of line and load variability.

Now that the phase loss is known the required amount of phase boost to meet the phase margin requirement can be determined. The required phase boost is given by Equation 22.

Equation 22.

P B = (P M - 90 d e g) - P L

Where PM = the desired phase margin.

A zero, pole pair of the compensation network is placed symmetrically around the intended closed-loop frequency to provide maximum phase boost at the crossover point. The amount of separation can be determined by Equation 23 and the resultant zero and pole frequencies are given by Equation 24 and Equation 25.

Equation 23.

k = t a n (\frac{P B}{2} + 45 d e g)

Equation 24.

F_{Z 1} = \frac{F_{C O}}{k}

Equation 25.

F_{P 1} = F_{C O} \times k

The low-frequency pole is set so that the gain at the crossover frequency is equal to the inverse of the gain of the modulator and output filter. Due to the relationships established by the pole and zero relationships, the value of R_Z can be derived directly by Equation 26.

Equation 26.

R_{Z} = \frac{2 \times π \times F_{C O} \times V_{O} \times C_{O} \times R_{O A}}{{G M}_{C O M P} \times V_{G G M} \times V_{R E F}}

Where:

V_O = Output voltage

C_O = Output capacitance

F_CO = Desired crossover frequency

R_OA = 8.696 MΩ

GM_COMP = 12 A/V

V_GGM = 800

V_REF = 0.8 V

With R_Z known, C_Z and C_P can be calculated using Equation 27 and Equation 28.

Equation 27.

C_{Z} = \frac{1}{2 \times π \times F_{Z 1} \times R_{Z}}

Equation 28.

C_{P} = \frac{1}{2 \times π \times F_{P 1} \times R_{Z}}

For this design, the two 47-μF output capacitors are used. For ceramic capacitors, the actual output capacitance is less than the rated value when the capacitors have a DC bias voltage applied. This is the case in a DC/DC converter. The actual output capacitance can be as low as 54 μF. The combined ESR is approximately 0.001 Ω.

Using Equation 20 and Equation 21, the output stage gain and phase loss are equivalent as:

Gain = –6.94 dB

and

PL = –93.94 degrees

For 70 degrees of phase margin, Equation 22 requires 63.64 degrees of phase boost.

Equation 23, Equation 24, and Equation 25 are used to find the zero and pole frequencies of:

F_Z1 = 11.57 kHz

And

F_P1 = 216 kHz

R_Z, C_Z, and C_P are calculated using Equation 26, Equation 27, and Equation 28.

Equation 29.

R_{Z} = \frac{2 \times π \times 50000 \times 2.5 \times 82 \times 10^{- 6} \times 8.696 \times 10^{6}}{12 \times 800 \times 0.8} = 72.92 k Ω

Equation 30.

C_{Z} = \frac{1}{2 \times π \times 11570 \times 75000} = 183 p F

Equation 31.

C_{P} = \frac{1}{2 \times π \times 216000 \times 75000} = 9.8 p F

Using standard values for R3, C6, and C7 in the application schematic of Figure 8-1.

R3 = 75 kΩ

C6 = 180 pF

C7 = 10 pF