SLUSC26A May   2015  – February 2016 TPS54334

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Light Load Operation
      3. 7.3.3  Slope Compensation and Output Current
      4. 7.3.4  Bootstrap Voltage (BOOT) and Low Dropout Operation
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Voltage Reference
      7. 7.3.7  Adjusting the Output Voltage
      8. 7.3.8  Enable and Undervoltage Lockout
      9. 7.3.9  Slow Start
      10. 7.3.10 Safe Start-up into Pre-Biased Outputs
      11. 7.3.11 Power Good (PGOOD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Overcurrent/Overvoltage/Thermal Protection
      2. 7.4.2 Thermal Shutdown
      3. 7.4.3 Small Signal Model for Loop Response
      4. 7.4.4 Small Signal Model for Peak Current Mode Control
      5. 7.4.5 Small Signal Model for Frequency Compensation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS54334 Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Switching Frequency
          2. 8.2.1.2.2 Output Voltage Set Point
          3. 8.2.1.2.3 Undervoltage Lockout Set Point
          4. 8.2.1.2.4 Input Capacitors
          5. 8.2.1.2.5 Output Filter Components
            1. 8.2.1.2.5.1 Inductor Selection
            2. 8.2.1.2.5.2 Capacitor Selection
          6. 8.2.1.2.6 Compensation Components
          7. 8.2.1.2.7 Bootstrap Capacitor
          8. 8.2.1.2.8 Power Dissipation Estimate
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connection. the VIN pin, and the GND pin of the IC. The typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN and GND pins of the device. See Figure 34 for a PCB layout example. The GND pin should be tied to the PCB ground plane at the pin of the IC. To facilitate close placement of the input bypass capacitors, The SW pin should be routed to a small copper area directly adjacent to the pin. Use vias to rout the SW signal to the bottom side or an inner layer. If necessary you can allow the top side copper area to extend slightly under the body of the closest input bypass capacitor. Make the copper trace on the bottom or internal layer short and wide as practical to reduce EMI issues. Connect the trace with vias back to the top side to connect with the output inductor as shown after the GND pin. In the same way use a bottom or internal layer trace to rout the SW signal across the VIN pin to connect to the BOOT capacitor as shown. Make the circulating loop from SW to the output inductor, output capacitors and back to GND as tight as possible while preserving adequate etch width to reduce conduction losses in the copper.

For operation at full rated load, the ground area near the IC must provide adequate heat dissipating area. Connect the exposed thermal pad to bottom or internal layer ground plane using vias as shown. Additional vias may be used adjacent to the IC to tie top side copper to the internal or bottom layer copper. The additional external components can be placed approximately as shown. Use a separate ground trace to connect the feedback, compensation, UVLO and RT returns. Connect this ground trace to the main power ground at a single point to minimize circulating currents. It may be possible to obtain acceptable performance with alternate layout schemes, however this layout has been shown to produce good results and is intended as a guideline.

10.2 Layout Example

TPS54334 layout_SLUSC26.gif Figure 34. TPS54334DDA Board Layout