JAJSCB1 July   2016 TPS54335-2A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Light-Load Operation
      3. 7.3.3  Voltage Reference
      4. 7.3.4  Adjusting the Output Voltage
      5. 7.3.5  Enabling and Adjusting Undervoltage Lockout
      6. 7.3.6  Error Amplifier
      7. 7.3.7  Slope Compensation and Output Current
      8. 7.3.8  Safe Startup into Pre-Biased Outputs
      9. 7.3.9  Bootstrap Voltage (BOOT)
      10. 7.3.10 Output Overvoltage Protection (OVP)
      11. 7.3.11 Overcurrent Protection
        1. 7.3.11.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.11.2 Low-Side MOSFET Overcurrent Protection
      12. 7.3.12 Thermal Shutdown
      13. 7.3.13 Small-Signal Model for Loop Response
      14. 7.3.14 Simple Small-Signal Model for Peak Current-Mode Control
      15. 7.3.15 Small-Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VI < 4.5 V (minimum VI)
      2. 7.4.2 Operation With EN Control
      3. 7.4.3 Operation With EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Supplementary Guidance
      2. 8.1.2 The DRC Package
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency
        2. 8.2.2.2 Output Voltage Set Point
        3. 8.2.2.3 Undervoltage Lockout Set Point
        4. 8.2.2.4 Input Capacitors
        5. 8.2.2.5 Output Filter Components
          1. 8.2.2.5.1 Inductor Selection
          2. 8.2.2.5.2 Capacitor Selection
        6. 8.2.2.6 Compensation Components
        7. 8.2.2.7 Bootstrap Capacitor
        8. 8.2.2.8 Power Dissipation Estimate
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 関連リンク
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 商標
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DRC Package
10-Pin VSON With Exposed Thermal Pad
Top View
TPS54335-2A drc_10_lusck3.gif

Pin Functions

PIN I/O DESCRIPTION
NAME VSON
BOOT 9 O A bootstrap capacitor is required between the BOOT and PH pins. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
COMP 7 O This pin is the error-amplifier output and the input to the output switch-current comparator. Connect frequency compensation components to this pin.
EN 8 I This pin is the enable pin. Float the EN pin to enable.
NC 2 — No Connect
GND 4 — Ground
GND 5 — Ground
PH 3 O The PH pin is the source of the internal high-side power MOSFET.
RT 10 O Connect the RT pin to an external timing resistor to adjust the switching frequency of the device.
VIN 1 — This pin is the 4.5-V to 28-V input supply voltage.
VSENSE 6 I This pin is the inverting node of the transconductance (gm) error amplifier.
Thermal pad — For proper operation, connect the GND pin to the exposed thermal pad. This thermal pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance.