10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade performance. To reduce parasitic effects, the VIN pin must be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care must be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 53 for a PCB layout example. The GND pin must be tied directly to the power pad under the IC and the power pad.

The power pad must be connected to internal PCB ground planes using multiple vias directly under the IC. The SW pin must be routed to the cathode of the catch diode and to the output inductor. Because the SW connection is the switching node, the catch diode and output inductor must be located close to the SW pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT resistor must be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. Obtaining acceptable performance with alternate PCB layouts is possible, however this layout has been shown to produce good results and is meant as a guideline.

10.2 Layout Example

Figure 53. PCB Layout Example

10.3 Estimated Circuit Area

Boxing in the components in the design of Figure 33 the estimated printed circuit board area is 1.025 in² (661 mm²). This area does not include test points or connectors.