11.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade performance.

• To reduce parasitic effects, bypass the VIN pin to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
• Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode.
• Tie the GND pin directly to the power pad under the IC and the PowerPAD.
• Connect the PowerPAD to internal PCB ground planes using multiple vias directly under the device. Route the SW pin to the cathode of the catch diode and to the output inductor.
• Because the SW connection is the switching node, the catch diode and output inductor must be located close to the SW pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
• For operation at full rated load, the top-side ground area must provide adequate heat dissipating area.
• The RT/CLK pin is sensitive to noise so place the RT resistor as close as possible to the IC and routed with minimal lengths of trace.
• The additional external components can be placed approximately as shown.
• Acceptable performance can be attained with alternate PCB layouts; however, this layout has been shown to produce good results and is meant as a guideline.