SLVSCC4B April   2014  – January 2017 TPS54361-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse-Skip Eco-mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjust Undervoltage Lockout
      8. 7.3.8  Soft-Start/Tracking Pin (SS/TR)
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
      11. 7.3.11 Accurate Current-Limit Operation and Maximum Switching Frequency
      12. 7.3.12 Synchronization to RT/CLK Pin
      13. 7.3.13 Power Good (PWRGD Pin)
      14. 7.3.14 Overvoltage Protection
      15. 7.3.15 Thermal Shutdown
      16. 7.3.16 Small Signal Model for Loop Response
      17. 7.3.17 Simple Small Signal Model for Peak Current Mode Control
      18. 7.3.18 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with V(VIN) = < 4.5 V (Minimum V(VIN))
      2. 7.4.2 Operation with EN Control
      3. 7.4.3 Alternate Power Supply Topologies
        1. 7.4.3.1 Inverting Power Supply
        2. 7.4.3.2 Split Rail Power Supply
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH® Tools
        2. 8.2.2.2  Selecting the Switching Frequency
        3. 8.2.2.3  Output Inductor Selection (LO)
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Catch Diode
        6. 8.2.2.6  Input Capacitor
        7. 8.2.2.7  Slow-Start Capacitor
        8. 8.2.2.8  Bootstrap Capacitor Selection
        9. 8.2.2.9  Undervoltage Lockout Set Point
        10. 8.2.2.10 Output Voltage and Feedback Resistors Selection
        11. 8.2.2.11 Compensation
        12. 8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Dissipation Estimate
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
      2. 11.2.2 Custom Design with WEBENCH® Tools
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage VIN –0.3 65 V
EN –0.3 8.4
BOOT 73
FB –0.3 3
COMP –0.3 3
PWRGD –0.3 6
SS/TR –0.3 3
RT/CLK –0.3 3.6
Output voltage BOOT-SW 8 V
SW –0.6 65
SW, 5-ns Transient –7 65
SW, 10-ns Transient –2 65
Operating junction temperature –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V
Charged device model (CDM), per AEC-Q100-011 Corner pins (1, 5, 6, and 10) ±750 V
Other pins ±500
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V(VIN) Supply input voltage 4.5 60 V
VO Output voltage 0.8 58.8 V
IO Output current 0 3.5 A
TJ Junction Temperature –40 150 °C

6.4 Thermal Information

THERMAL METRIC(1)(2) TPS54361-Q1 UNIT
DPS (10 PINS)
RθJA Junction-to-ambient thermal resistance (standard board) 35.1 °C/W
ψJT Junction-to-top characterization parameter 0.3
ψJB Junction-to-board characterization parameter 12.5
RθJCtop Junction-to-case(top) thermal resistance 34.1
RθJCbot Junction-to-case(bottom) thermal resistance 2.2
RθJB Junction-to-board thermal resistance 12.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Power rating at a specific ambient temperature TA must be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. See the power dissipation estimate in the Power Dissipation Estimate section of this data sheet for more information.

6.5 Electrical Characteristics

TJ = –40°C to 150°C, V(VIN) = 4.5 V to 60 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 4.5 60 V
Internal undervoltage lockout threshold Rising 4.1 4.3 4.48 V
Internal undervoltage lockout threshold hysteresis 325 mV
Shutdown supply current V(EN) = 0 V, 25°C, 4.5 V ≤ V(VIN) ≤ 60 V 2.25 4.5 μA
Operating: nonswitching supply current V(FB) = 0.9 V, TA = 25°C 152 200
ENABLE AND UVLO (EN PIN)
V(EN)th Enable threshold voltage No voltage hysteresis, rising and falling 1.1 1.2 1.3 V
II Input current Enable threshold 50 mV –4.6 μA
Enable threshold –50 mV –0.58 –1.2 -1.8
Ihys Hysteresis current –2.2 –3.4 -4.5 μA
VOLTAGE REFERENCE
Voltage reference 0.792 0.8 0.808 V
HIGH-SIDE MOSFET
On-resistance V(VIN) = 12 V, V(BOOT-SW) = 6 V 87 185 mΩ
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gm) –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V 350 μMhos
Error amplifier transconductance (gm) during soft-start –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V, V(FB) = 0.4 V 77 μMhos
Error amplifier dc gain V(FB) = 0.8 V 10 000 V/V
Min unity gain bandwidth 2500 kHz
Error amplifier source/sink V(COMP) = 1 V, 100-mV overdrive ±30 μA
COMP to SW current transconductance 12 A/V
CURRENT-LIMIT
Current-limit threshold All VIN and temperatures, open loop(1) 4.5 5.5 6.8 A
All temperatures, V(VIN) = 12 V, open loop(1) 4.5 5.5 6.3
V(VIN) = 12 V, TA = 25°C, open loop(1) 5.2 5.5 5.9
THERMAL SHUTDOWN
Thermal shutdown 176 °C
Thermal shutdown hysteresis 12 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK high threshold 1.55 2 V
RT/CLK low threshold 0.5 1.2 V
SOFT START AND TRACKING (SS/TR PIN)
ISS Charge current V(SS/TR) = 0.4 V 1.7 µA
VSS(ofs) SS/TR-to-FB matching V(SS/TR) = 0.4 V 42 mV
SS/TR-to-reference crossover 98% nominal 1.16 V
SS/TR discharge current (overload) V(FB) = 0 V, V(SS/TR) = 0.4 V 354 µA
SS/TR discharge voltage V(FB) = 0 V 54 mV
POWER GOOD (PWRGD PIN)
FB threshold for PWRGD low FB falling 90%
FB threshold for PWRGD high FB rising 93%
FB threshold for PWRGD low FB rising 108%
FB threshold for PWRGD high FB falling 106%
Hysteresis FB falling 2.5%
Output high leakage V(PWRGD) = 5.5 V, TA = 25°C 10 nA
On resistance I(PWRGD) = 3 mA, V(FB) < 0.79 V 45 Ω
Minimum VIN for defined output V(PWRGD) < 0.5 V, I(PWRGD) = 100 µA 0.9 2 V
(1) Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.

6.6 Timing Requirements

MIN TYP MAX UNIT
RT/CLK
Minimum CLK input pulse width 15 ns

6.7 Switching Characteristics

TJ = –40°C to 150°C, V(VIN) = 4.5 V to 60 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ENABLE AND UVLO (EN PIN)
Enable to COMP active V(VIN) = 12 V, TA = 25°C 540 µs
CURRENT-LIMIT
Current limit threshold delay 60 ns
SW
ton Minimum on time V(VIN) = 23.7 V, VO = 5 V, IO = 3.5 A, R(RT) = 39.6 kΩ, TA = 25°C 100 ns
RT/CLK
Switching frequency range using RT mode 100 2500 kHz
ƒS Switching frequency R(RT) = 200 kΩ 450 500 550 kHz
Switching frequency range using CLK mode 160 2300 kHz
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK falling edge to SW rising edge delay Measured at 500 kHz with an RT resistor (R(RT)) in series 55 ns
PLL lock in time Measured at 500 kHz 78 μs

6.8 Typical Characteristics

TPS54361-Q1 D004_slvscc4.gif
Figure 1. On Resistance vs Junction Temperature
TPS54361-Q1 D027_slvscc4.gif
V(VIN) = 12 V
Figure 3. Switch Current-Limit vs Junction Temperature
TPS54361-Q1 D025_slvscc4.gif
V(VIN) = 12 V R(RT) = 200 kΩ
Figure 5. Switching Frequency vs Junction Temperature
TPS54361-Q1 D023_slvscc4.gif
Figure 7. Switching Frequency vs RT/CLK Resistance
High Frequency Range
TPS54361-Q1 D021_slvscc4.gif
V(VIN) = 12 V
Figure 9. EA Transconductance During Soft-Start vs Junction Temperature
TPS54361-Q1 D019_slvscc4.gif
V(VIN) = 12 V V(EN) = Threshold + 50 mV
Figure 11. EN Pin Current vs Junction Temperature
TPS54361-Q1 D017_slvscc4.gif
V(VIN) = 12 V
Figure 13. EN Pin Current Hysteresis vs Junction Temperature
TPS54361-Q1 D015_slvscc4.gif
V(VIN) = 12 V
Figure 15. Shutdown Supply Current vs Junction Temperature
TPS54361-Q1 D013_slvscc4.gif
V(VIN) = 12 V
Figure 17. I(VIN) Supply Current vs Junction Temperature
TPS54361-Q1 D011_slvscc4.gif
Figure 19. BOOT-SW UVLO vs Junction Temperature
TPS54361-Q1 D009_slvscc4.gif
V(VIN) = 12 V
Figure 21. PWRGD On Resistance vs Junction Temperature
TPS54361-Q1 D007_slvscc4.gif
V(VIN) = 12 V 25°C
Figure 23. SS/TR to FB Offset vs FB
TPS54361-Q1 D005_slvscc4.gif
Figure 25. 5-V Start and Stop Voltage (see Low Dropout Operation and Bootstrap Voltage (BOOT))
TPS54361-Q1 D028_slvscc4.gif
V(VIN) = 12 V
Figure 2. Voltage Reference vs Junction Temperature
TPS54361-Q1 D026_slvscc4.gif
Figure 4. Switch Current-Limit vs Input Voltage
TPS54361-Q1 D024_slvscc4.gif
Figure 6. Switching Frequency vs RT/CLK Resistance
Low Frequency Range
TPS54361-Q1 D022_slvscc4.gif
V(VIN) = 12 V
Figure 8. EA Transconductance vs Junction Temperature
TPS54361-Q1 D020_slvscc4.gif
V(VIN) = 12 V
Figure 10. EN Pin Voltage vs Junction Temperature
TPS54361-Q1 D018_slvscc4.gif
V(VIN) = 12 V V(EN) = Threshold – 50 mV
Figure 12. EN Pin Current vs Junction Temperature
TPS54361-Q1 D016_SLVSCC4.gif
Figure 14. Switching Frequency vs FB
TPS54361-Q1 D014_slvscc4.gif
TJ = 25 °C
Figure 16. Shutdown Supply Current vs Input Voltage
TPS54361-Q1 D012_slvscc4.gif
TJ = 25°C
Figure 18. I(VIN) Supply Current vs Input Voltage
TPS54361-Q1 D010_slvscc4.gif
Figure 20. Input Voltage UVLO vs Junction Temperature
TPS54361-Q1 D008_slvscc4.gif
V(VIN) = 12 V
Figure 22. PWRGD Threshold vs Junction Temperature
TPS54361-Q1 D006_slvscc4.gif
V(VIN) = 12 V V(FB) = 0.4 V
Figure 24. SS/TR to FB Offset vs Temperature