The TPS54361 device is a 60-V, 3.5-A, step-down regulator with an integrated high-side MOSFET. The device survives load dump pulses up to 65 V per ISO 7637. Current-mode control provides simple external compensation and flexible component selection. A low-ripple pulse-skip mode reduces the no-load supply current to 152 μA. Shutdown supply current is reduced to 2 μA when the enable pin is pulled low.
Undervoltage lockout is internally set at 4.3 V but can increase using an external resistor-divider at the enable pin. The output voltage startup ramp is controlled by the soft-start pin that can also be configured for sequencing and tracking. An open-drain power-good signal indicates the output is within 93% to 106% of the nominal voltage.
A wide adjustable switching frequency range allows for optimization of either efficiency or external component size. Cycle-by-cycle current limit, frequency foldback, and thermal shutdown protects internal and external components during an overload condition.
The TPS54361 device is available in a 10-pin 4-mm × 4-mm WSON package.
PART NUMBER | PACKAGE (PIN) | BODY SIZE |
---|---|---|
TPS54361 | WSON (10) | 4.00 mm × 4.00 mm |
Changes from C Revision (February 2016) to D Revision
Changes from B Revision (August 2015) to C Revision
Changes from A Revision (December 2013) to B Revision
Changes from * Revision (November 2013) to A Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
BOOT | 1 | I | A bootstrap capacitor is required between the BOOT and SW pin. If the voltage on this capacitor is below the minimum required to turn on the high-side MOSFET, the gate drive is switched off until the capacitor is refreshed. | |
COMP | 7 | I | This pin is the error amplifier output and input to the output switch current (PWM) comparator. Connect frequency compensation components to this pin. | |
EN | 3 | I | This pin is the enable pin. An internal pullup current source enables the TPS54361 if the EN pin is floating. Pull EN below 1.2 V to disable. Adjust the input undervoltage lockout with two resistors. See Enable and Adjusting Undervoltage Lockout. | |
FB | 6 | I | This pin is the inverting input of the transconductance (gm) error amplifier. | |
GND | 8 | – | Ground | |
PWRGD | 10 | O | The Power Good pin is an open drain output that asserts low if the output voltage is out of regulation because of thermal shutdown, dropout, overvoltage, or EN shutdown. | |
RT/CLK | 5 | I | This pin is the resistor timing and external clock pin. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high-impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming. | |
SS/TR | 4 | I | This pin is the soft start and tracking pin. An external capacitor connected to this pin sets the output rise time. Because the voltage on this pin overrides the internal reference, the SS/TR pin can be used for tracking and sequencing. | |
SW | 9 | O | The SW pin is the source of the internal high-side power MOSFET and switching node of the converter. | |
VIN | 2 | I | Connect to this pin the input voltage supply with a 4.5-V to 60-V operating range. | |
Thermal Pad | – | The GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. |