JAJSJT8C May 2020 – June 2021 TPS543620
PRODUCTION DATA
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
SYNC/FSEL | 1 | I | Frequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the switching frequency. |
MODE | 2 | I | A resistor to ground selects the current limit, soft start rate, and PWM ramp amplitude. |
PGOOD | 3 | O | Open-drain power good indicator |
FB | 4 | I | Feedback pin for output voltage regulation. Connect this pin to the midpoint of a resistor divider to set the output voltage. |
AGND | 5 | - | Ground return for internal analog circuits |
BP5 | 6 | O | Internal 4.5-V regulator output. Bypass this pin with a 2.2-μF capacitor to AGND. |
EN | 7 | I | Enable pin. Float to enable, enable/disable with an external signal, or adjust the input undervoltage lockout with a resistor divider. |
VIN | 8, 12 | I | Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 10-nF to 100-nF capacitor from each VIN to PGND close to IC is required. |
PGND | 9, 11 | - | Ground return for the power stage. This pin is internally connected to the source of the low-side MOSFET. |
SW | 10 | O | Switch node of the converter. Connect this pin to the output inductor. |
SW | 13 | O | Return path for the internal high-side MOSFET gate driver bootstrap capacitor. Connect a capacitor from BOOT to this pin. The SW pins are connected internally. |
BOOT | 14 | I | Supply for the internal high-side MOSFET gate driver. Connect a capacitor from this pin to SW. |