JAJSPW0B June 2023 – June 2024 TPS543B25T
PRODUCTION DATA
A 2.2µF ceramic capacitor must be connected between the VDRV pin and PGND for proper operation. The capacitor must be rated for at least 10V to minimize DC bias derating. The VDRV pin is the output of an internal linear regulator and the supply to the gate drivers. The VCC pin is the supply for the analog control circuits and must have a 0.1µF and 10V rated or better ceramic capacitor connected from VCC to AGND. A 10Ω 0402 resistor must be connected between the VDRV to VCC pins.