TPS544C26 device supports adaptive voltage positioning (AVP) through DC Load Line (DCLL) setting in the (ADh) COMP3 register. Use a non-zero DC load line reduces output voltage set-point as a function of the load current, with a controlled slope. This feature is optional and the DCLL setting usually matches what the processor suggests. If a processor doesn’t utilize Droop, setting DCLL to 0 mΩ is recommended to avoid violating the VOUT tolerance band spec of the processor.

The DC load line provides two main benefits:

• Reducing the output voltage set-point, reduces the power consumption of the system, when the load current is high.
• Adaptive voltage positioning increases the allowable undershoot and overshoot during load transient events. Below figure compares example output voltage specifications for systems with zero load line and non-zero load line. The nominal setting for the output voltage is chosen to be higher, to allow the entire transient window as margin for transient overshoot and undershoot.