JAJSP58 September 2022 TPS544C26
ADVANCE INFORMATION
| CMD Address | 80h |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| NVM Backup: | No |
| Updates: | On-the-fly |
The STATUS_MFR_SPECIFIC command returns one data byte with contents as follows. All supported bits, except DCM bit, can be cleared either by CLEAR_FAULTS, or individually by writing a "1" to the (80h) STATUS_MFR_SPECIFIC register in their position. If a fault condition is still present when the corresponding bit is cleared, the fault bit is immediately set again.
Bit[7] DCM is a LIVE bit updated by the analog detection circuit, which continuously monitors the output of the zero-cross comparator. During CCM operation, this bit shows a value of "0". Once the device enters DCM operation this bit is set showing a value of "1".
Return to Supported I2C and Default Values.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| DCM | OTF_ANALOG | PS_FAULT | PS_COMM_WRN | RESTORE_ERR | NOC | PS_OTF_ANALOG | VDRV_UVF |
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7 | DCM | R/W | 0b | A LIVE bit updated by the analog detection circuit, which
continuously monitors the output of the zero-cross comparator.
0b: Un-latched flag indicating the the device is under CCM operation. 1b: Un-latched flag indicating the the device is under DCM operation. |
| 6 | OTF_ANALOG | R/W | 0b | 0b: Latched flag indicating an OT fault has not occurred. 1b: Latched flag indicating an OT fault has occurred on the Controller die. Note: An analog comparator on the Controller die is utilized to compare the output of the IC temperature sensing circuit to a fixed threshold (166 °C typical). This bit has no relationship with the overtemperature detection implemented on the Power Stage (PS) die. |
| 5 | PS_FAULT | R/W | 0b |
0b: Latched flag indicating no fault has occurred on Power Stage (PS) die. 1b: Latched flag indicating at least one fault has occurred on the PS die. |
| 4 | PS_COMM_WRN | R/W | 0b | 0b: Latched flag indicating no error has occurred for the communications between the Controller and PS die. 1b: Latched flag indicating a communications error has occurred between the Controller and PS die. Note: A VCC reset (power cycle) is recommended when this bit is set. |
| 3 | RESTORE_ERR | R/W | 0b: | 0b: Latched flag indicating no error has occurred during the initial restore from NVM operation (copy the entire contents of the non-volatile User Store Memory to the matching locations in the Operating Memory). 1b: Latched flag indicating an error has occurred during the initial restore from NVM operation. Note: The restore operation mentioned here refers to the one-time restore operation during the initial power-on. This bit doesn't validate the RESTORE_USER_ALL operation. A VCC reset (power cycle) is recommended when this bit is set. |
| 2 | NOC | R/W | 0b |
0b: Latched flag indicating no NOC operation has occurred. 1b: Latched flag indicating at least one cycle of NOC operation has occurred. |
| 1 | PS_OTF_ANALOG | R/W | 0b | 0b: Un-latched flag indicating an OT fault has not occurred. 1b: Un-latched flag indicating an OT fault has occurred on the Power Stage (PS) die. Note: An analog comparator on the Power Stage die is utilized to compare the output of the IC temperature sensing circuit to a fixed threshold (166 °C typical). This bit has no relationship with the overtemperature detection implemented on the Controller die. |
| 0 | VDRV_UVF | R/W | 0b |
0b: Latched flag indicating a VDRV UV fault has not occurred. 1b: Latched flag indicating a VDRV UV fault has occurred. |