SLUSF22 November   2024 TPS54538

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Fixed Frequency Peak Current Mode
      2. 6.3.2  Mode Selection
      3. 6.3.3  Voltage Reference
      4. 6.3.4  Output Voltage Setting
      5. 6.3.5  Switching Frequency Selection / Synchronization
      6. 6.3.6  Phase Shift
      7. 6.3.7  Enable and Adjusting Undervoltage Lockout
      8. 6.3.8  External Soft Start and Prebiased Soft Start
      9. 6.3.9  Power Good
      10. 6.3.10 Minimum On Time, Minimum Off Time, and Frequency Foldback
      11. 6.3.11 Frequency Spread Spectrum
      12. 6.3.12 Overvoltage Protection
      13. 6.3.13 Overcurrent and Undervoltage Protection
      14. 6.3.14 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes Overview
      2. 6.4.2 Heavy Load Operation
      3. 6.4.3 Pulse Frequency Modulation
      4. 6.4.4 Forced Continuous Conduction Modulation
      5. 6.4.5 Dropout Operation
      6. 6.4.6 Minimum On-Time Operation
      7. 6.4.7 Shutdown Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 Output Voltage Resistors Selection
        3. 7.2.2.3 Choosing Switching Frequency
        4. 7.2.2.4 Soft-Start Capacitor Selection
        5. 7.2.2.5 Output Inductor Selection
        6. 7.2.2.6 Output Capacitor Selection
        7. 7.2.2.7 Input Capacitor Selection
        8. 7.2.2.8 Feedforward Capacitor CFF Selection
        9. 7.2.2.9 Maximum Ambient Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.9 Power Good

When the TPS54538 is configured to PG function, the SS/PG pin is used to indicate whether the output voltage has reached the appropriate level or not. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is an open-drain output that requires a pullup resistor to any voltage below 5.5V. TI recommends a pullup resistor of 10kΩ – 100kΩ. The device can sink approximately 4mA of current and maintain the specified logic low level. After the FB pin voltage is between 90% and 107% of the internal reference voltage (VREF) and after a deglitch time of 70μs, the PG turns to high impedance status. The PG pin is pulled low after a deglitch time of 13μs when FB pin voltage is lower than 85% of the internal reference voltage or greater than 115% of the internal reference voltage, or in events of thermal shutdown, EN shutdown, or UVLO conditions. VIN must remain present for the PG pin to stay low.

Table 6-4 PG Status
Device StatePG Logic Status
High ImpedanceLow
Enable (EN = High)VFB does not trigger VPGTH√
VFB triggers VPGTH√
Shutdown (EN = Low)√
UVLO2.5V < VIN < VUVLO√
Thermal shutdownTJ > TSD√
Power supply removalVIN < 2.5V√