SLUSF22 November   2024 TPS54538

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Fixed Frequency Peak Current Mode
      2. 6.3.2  Mode Selection
      3. 6.3.3  Voltage Reference
      4. 6.3.4  Output Voltage Setting
      5. 6.3.5  Switching Frequency Selection / Synchronization
      6. 6.3.6  Phase Shift
      7. 6.3.7  Enable and Adjusting Undervoltage Lockout
      8. 6.3.8  External Soft Start and Prebiased Soft Start
      9. 6.3.9  Power Good
      10. 6.3.10 Minimum On Time, Minimum Off Time, and Frequency Foldback
      11. 6.3.11 Frequency Spread Spectrum
      12. 6.3.12 Overvoltage Protection
      13. 6.3.13 Overcurrent and Undervoltage Protection
      14. 6.3.14 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes Overview
      2. 6.4.2 Heavy Load Operation
      3. 6.4.3 Pulse Frequency Modulation
      4. 6.4.4 Forced Continuous Conduction Modulation
      5. 6.4.5 Dropout Operation
      6. 6.4.6 Minimum On-Time Operation
      7. 6.4.7 Shutdown Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 Output Voltage Resistors Selection
        3. 7.2.2.3 Choosing Switching Frequency
        4. 7.2.2.4 Soft-Start Capacitor Selection
        5. 7.2.2.5 Output Inductor Selection
        6. 7.2.2.6 Output Capacitor Selection
        7. 7.2.2.7 Input Capacitor Selection
        8. 7.2.2.8 Feedforward Capacitor CFF Selection
        9. 7.2.2.9 Maximum Ambient Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.2.6 Output Capacitor Selection

The device is designed to be used with a wide variety of LC filters, so using as little output capacitance as possible to keep cost and size down is desired. Choose the output capacitance, COUT, with care because the output capacitance directly affects the following specifications:

  • Steady state output voltage ripple
  • Loop stability
  • Output voltage overshoot and undershoot during load current transient

The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the Equivalent Series Resistance (ESR) of the output capacitors:

Equation 20. ∆ V O U T _ E S R = ∆ I L × E S R = K × I O U T × E S R

The other is caused by the inductor current ripple charging and discharging the output capacitors:

Equation 21. ∆ V O U T _ C = ∆ I L 8 × f S W × C O U T = K × I O U T 8 × f S W × C O U T

where

  • K is the ripple ratio of the inductor current (ΔIL / IOUT_MAX).

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of the two peaks.

Output capacitance is usually limited by the load transient requirements rather than the output voltage ripple if the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a large load step happens, output capacitors provide the required charge before the inductor current can slew up to the appropriate level. The control loop of the converter usually needs eight or more clock cycles to regulate the inductor current equal to the new load level. The output capacitance must be large enough to supply the current difference for about eight clock cycles to maintain the output voltage within the specified range. Equation 22 shows the minimum output capacitance needed for specified VOUT overshoot and undershoot.

Equation 22. C O U T > 1 2 × ∆ I O U T ∆ V O U T _ S H O O T ( 6 f S W - 1 S R ∆ I O U T )

where

  • D is VOUT / VIN, duty cycle of steady state.
  • ΔVOUT_SHOOT is the output voltage change.
  • ΔIOUT is the output current change.
  • SRΔIOUT is the slew rate of output current change

For this design example, the target output ripple is 30mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 30mV and choose K = 0.3. Equation 20 yields ESR no larger than 25mΩ and Equation 21 yields COUT no smaller than 10μF. For the overshoot and undershoot limitation of this design, ΔVOUT_SHOOT < 5% × VOUT = 250mV for an output current step of ΔIOUT = 4A with SRΔIOUT = 0.8A/μs. COUT is calculated to be no smaller than 38μF by Equation 22. In summary, the most stringent criterion for the output capacitor is 38μF. By considering the ceramic capacitor has DC bias derating, it can be achieved with a bank of 2 × 22μF, 35V, ceramic capacitor C3216X5R1V226M160AC in the 1206 case size.

More output capacitors can be used to improve the load transient response. Ceramic capacitors can easily meet the minimum ESR requirements. In some cases, an aluminum electrolytic capacitor can be placed in parallel with the ceramics to build up the required value of capacitance. When using a mixture of aluminum and ceramic capacitors, use the minimum recommended value of ceramics and add aluminum electrolytic capacitors as needed.

The recommendations given in Table 7-2 provide typical values of output capacitance for the given conditions. Large values of output capacitance can adversely affect the start-up behavior of the converter as well as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load and loop stability must be performed.

In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load transient testing and bode plots are the best way to validate any given design and must always be completed before the application goes into production. In addition to the required output capacitance, a small ceramic placed on the output can reduce high frequency noise. Small case size ceramic capacitors in the range of 1nF to 100nF can help reduce spikes on the output caused by inductor and board parasitics.

Table 7-2 shows the recommended LC combination.

Table 7-2 Recommended LC Combination for TPS54538
VOUT(V) fSW (kHz) RTOP(kΩ) RDOWN(kΩ) Typical Inductor L (μH) Typical COUT (μF)
3.3 500 45 10.0 4.7 44
1000 1.5 44
5 500 73.3 10.0 5.6 44
1000 2.2 44
12 500 190 10.0 5.6 66