JAJSIO4A February 2020 – September 2020 TPS546A24A
PRODUCTION DATA
CMD Address | 22h |
Write Transaction: | Write Word |
Read Transaction: | Read Word |
Format: | SLINEAR16, Absolute Only per Section 7.6.18. |
Phased: | No |
NVM Back-up: | EEPROM |
Updates: | on-the-fly |
VOUT_TRIM is used to apply a fixed offset voltage to the output voltage command value. Output voltage changes due to Section 7.5.2.3 occur at the rate specified by Section 7.6.24.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RW | RW | RW | RW | RW | RW | RW | RW |
VOUT_TRIM (High Byte) | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RW | RW | RW | RW | RW | RW | RW | RW |
VOUT_TRIM (Low Byte) |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | Access | Reset | Description |
---|---|---|---|---|
15:0 | VOUT_ TRIM | RW | See Below | Output voltage offset. SLINEAR16 (two’s complement) format |
Limited NVM Back-up
Only 8 bits of NVM backup are provided for this command. While the Section 7.5.2.3 command follows the Section 7.6.18 exponent, NVM back-up is stored with an exponent -12 and stored values will be limited to -127 to +127 with an exponent -12 (-31mV to +31mV) irrespective of Section 7.6.18.
Data Validity
VOUT_TRIM will accept valies from -127 to +127 with the current Section 7.6.18, but the NVM stored value will be limited as above. Values beyond this range will be NACKed and reported as invalid data in Section 7.6.60.
Referring to the data validity table in Section 7.6.19 (reproduced below), the output voltage value (including any offset from Section 7.5.2.3, Section 7.6.19, VOUT_MARGIN, …) may not exceed the values supported by the DAC hardware.
Programming a Section 7.6.19 + Section 7.6.20 value greater than the maximum value supported by the DAC hardware but less than Section 7.6.21 will result in the regulated output voltage clamping at the maximum value supported by the DAC hardware without setting the VOUT_MAX_MIN bit in Section 7.6.56.
VOUT_SCALE _LOOP | INTERNAL DIVIDER | VALID VOUT_COMMAND /MARGIN + VOUT_TRIM VALUES |
---|---|---|
1.0 | None | 0.000V to 0.700 V |
0.5 | 1:1 | 0.000 V to 1.400 V |
0.25 | 1:3 | 0.000 V to 2.800 V |
0.125 | 1:7 | 0.000 V to 6.000 V |
The minimum and maximum valid data values for Section 7.5.2.3 follow the description in Section 7.6.19. Attempts to write Section 7.5.2.3 to any value outside those specified as valid, will be considered invalid/unsupported data and cause the TPS546A24A to respond by flagging the appropriate status bits, and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.
Writes to Section 7.5.2.3 for which the resulting output voltage is greater than the current Section 7.6.21, or less than the current Section 7.6.26, cause the reference DAC to move to the value specified by Section 7.6.26 or Section 7.6.21, respectively, and cause the VOUT_MAX_MIN_WARNING fault condition, setting the appropriate bits in Section 7.6.55, Section 7.6.56 and notifying the host per the PMBus 1.3.1 Part II specification, section 10.2.