JAJSIO4A
February 2020 – September 2020
TPS546A24A
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Average Current-Mode Control
7.3.1.1
On-Time Modulator
7.3.1.2
Current Error Integrator
7.3.1.3
Voltage Error Integrator
7.3.2
Linear Regulators
7.3.3
AVIN and PVIN Pins
7.3.4
Input Undervoltage Lockout (UVLO)
7.3.4.1
Fixed AVIN UVLO
7.3.4.2
Fixed VDD5 UVLO
7.3.4.3
Programmable PVIN UVLO
7.3.4.4
EN/UVLO Pin
7.3.5
Start-Up and Shutdown
7.3.6
Differential Sense Amplifier and Feedback Divider
7.3.7
Set Output Voltage and Adaptive Voltage Scaling (AVS)
7.3.7.1
Reset Output Voltage
7.3.7.2
Soft Start
7.3.8
Prebiased Output Start-Up
7.3.9
Soft Stop and (65h) TOFF_FALL Command
7.3.10
Power Good (PGOOD)
7.3.11
Set Switching Frequency
7.3.12
Frequency Synchronization
7.3.13
Loop Slave Detection
7.3.14
Current Sensing and Sharing
7.3.15
Telemetry
7.3.16
Overcurrent Protection
7.3.17
Overvoltage/Undervoltage Protection
7.3.18
Overtemperature Management
7.3.19
Fault Management
7.3.20
Back-Channel communication
7.3.21
Switching Node (SW)
7.3.22
PMBus General Description
7.3.23
PMBus Address
7.3.24
PMBus Connections
7.4
Device Functional Modes
7.4.1
Programming Mode
7.4.2
StandAlone/Master/Slave Mode Pin Connections
7.4.3
Continuous Conduction Mode
7.4.4
Operation With CNTL Signal (EN/UVLO)
7.4.5
Operation with Control
7.4.6
Operation with CNTL and Control
7.5
Programming
7.5.1
Supported PMBus Commands
7.5.2
Pin Strapping
7.5.2.1
Programming MSEL1
7.5.2.2
Programming MSEL2
7.5.2.3
Programming VSEL
7.5.2.4
Programming ADRSEL
7.5.2.5
Programming MSEL2 for a Slave Device (GOSNS Tied to BP1V5)
7.5.2.6
Pin-Strapping Resistor Configuration
7.6
Register Maps
7.6.1
Conventions for Documenting Block Commands
7.6.2
(01h) OPERATION
7.6.3
(02h) ON_OFF_CONFIG
7.6.4
(03h) CLEAR_FAULTS
7.6.5
(04h) PHASE
7.6.6
(10h) WRITE_PROTECT
7.6.7
(15h) STORE_USER_ALL
7.6.8
(16h) RESTORE_USER_ALL
7.6.9
(19h) CAPABILITY
7.6.10
(1Bh) SMBALERT_MASK
7.6.11
(1Bh) SMBALERT_MASK_VOUT
7.6.12
(1Bh) SMBALERT_MASK_IOUT
7.6.13
(1Bh) SMBALERT_MASK_INPUT
7.6.14
(1Bh) SMBALERT_MASK_TEMPERATURE
7.6.15
(1Bh) SMBALERT_MASK_CML
7.6.16
(1Bh) SMBALERT_MASK_OTHER
7.6.17
(1Bh) SMBALERT_MASK_MFR
7.6.18
(20h) VOUT_MODE
7.6.19
(21h) VOUT_COMMAND
7.6.20
(22h) VOUT_TRIM
7.6.21
(24h) VOUT_MAX
7.6.22
(25h) VOUT_MARGIN_HIGH
7.6.23
(26h) VOUT_MARGIN_LOW
7.6.24
(27h) VOUT_TRANSITION_RATE
7.6.25
(29h) VOUT_SCALE_LOOP
7.6.26
(2Bh) VOUT_MIN
7.6.27
(33h) FREQUENCY_SWITCH
7.6.28
(35h) VIN_ON
7.6.29
(36h) VIN_OFF
7.6.30
(37h) INTERLEAVE
7.6.31
(38h) IOUT_CAL_GAIN
7.6.32
(39h) IOUT_CAL_OFFSET
7.6.33
(40h) VOUT_OV_FAULT_LIMIT
7.6.34
(41h) VOUT_OV_FAULT_RESPONSE
7.6.35
(42h) VOUT_OV_WARN_LIMIT
7.6.36
(43h) VOUT_UV_WARN_LIMIT
7.6.37
(44h) VOUT_UV_FAULT_LIMIT
7.6.38
(45h) VOUT_UV_FAULT_RESPONSE
7.6.39
(46h) IOUT_OC_FAULT_LIMIT
7.6.40
(47h) IOUT_OC_FAULT_RESPONSE
7.6.41
(4Ah) IOUT_OC_WARN_LIMIT
7.6.42
(4Fh) OT_FAULT_LIMIT
7.6.43
(50h) OT_FAULT_RESPONSE
7.6.44
(51h) OT_WARN_LIMIT
7.6.45
(55h) VIN_OV_FAULT_LIMIT
7.6.46
(56h) VIN_OV_FAULT_RESPONSE
7.6.47
(58h) VIN_UV_WARN_LIMIT
7.6.48
(60h) TON_DELAY
7.6.49
(61h) TON_RISE
7.6.50
(62h) TON_MAX_FAULT_LIMIT
7.6.51
(63h) TON_MAX_FAULT_RESPONSE
7.6.52
(64h) TOFF_DELAY
7.6.53
(65h) TOFF_FALL
7.6.54
(78h) STATUS_BYTE
7.6.55
(79h) STATUS_WORD
7.6.56
(7Ah) STATUS_VOUT
7.6.57
(7Bh) STATUS_IOUT
7.6.58
(7Ch) STATUS_INPUT
7.6.59
(7Dh) STATUS_TEMPERATURE
7.6.60
(7Eh) STATUS_CML
7.6.61
(7Fh) STATUS_OTHER
7.6.62
(80h) STATUS_MFR_SPECIFIC
7.6.63
(88h) READ_VIN
7.6.64
(8Bh) READ_VOUT
7.6.65
(8Ch) READ_IOUT
7.6.66
(8Dh) READ_TEMPERATURE_1
7.6.67
(98h) PMBUS_REVISION
7.6.68
(99h) MFR_ID
7.6.69
(9Ah) MFR_MODEL
7.6.70
(9Bh) MFR_REVISION
7.6.71
(9Eh) MFR_SERIAL
7.6.72
(ADh) IC_DEVICE_ID
7.6.73
(AEh) IC_DEVICE_REV
7.6.74
(B1h) USER_DATA_01 (COMPENSATION_CONFIG)
7.6.75
(B5h) USER_DATA_05 (POWER_STAGE_CONFIG)
7.6.76
(D0h) MFR_SPECIFIC_00 (TELEMETRY_CONFIG)
7.6.77
(DAh) MFR_SPECIFIC_10 (READ_ALL)
7.6.78
(DBh) MFR_SPECIFIC_11 (STATUS_ALL)
7.6.79
(DCh) MFR_SPECIFIC_12 (STATUS_PHASE)
7.6.80
(E3h) MFR_SPECIFIC_19 (PGOOD_CONFIG)
7.6.81
(E4h) MFR_SPECIFIC_20 (SYNC_CONFIG)
7.6.82
(ECh) MFR_SPECIFIC_28 (STACK_CONFIG)
7.6.83
(EDh) MFR_SPECIFIC_29 (MISC_OPTIONS)
7.6.84
(EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE)
7.6.85
(EFh) MFR_SPECIFIC_31 (SLAVE_ADDRESS)
7.6.86
(F0h) MFR_SPECIFIC_32 (NVM_CHECKSUM)
7.6.87
(F1h) MFR_SPECIFIC_33 (SIMULATE_FAULT)
7.6.88
(FCh) MFR_SPECIFIC_44 (FUSION_ID0)
7.6.89
(FDh) MFR_SPECIFIC_45 (FUSION_ID1)
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Custom Design With WEBENCH® Tools
8.2.2.2
Switching Frequency
8.2.2.3
Inductor Selection
8.2.2.4
Output Capacitor Selection
8.2.2.4.1
Output Voltage Deviation During Load Transient
8.2.2.4.2
Output Voltage Ripple
8.2.2.5
Input Capacitor Selection
8.2.2.6
AVIN, BP1V5, VDD5 Bypass Capacitor
8.2.2.7
Bootstrap Capacitor Selection
8.2.2.8
R-C Snubber
8.2.2.9
Output Voltage Setting (VSEL Pin)
8.2.2.10
Compensation Selection (MSEL1 Pin)
8.2.2.11
Soft Start, Overcurrent Protection, and Stacking Configuration (MSEL2 Pin)
8.2.2.12
Enable and UVLO
8.2.2.13
ADRSEL
8.2.2.14
Pin-Strapping Resistor Selection
8.2.2.15
BCX_CLK and BCX_DAT
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
10.3
Mounting and Thermal Profile Recommendation
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.1.2
Development Support
11.1.2.1
Texas Instruments Fusion Digital Power Designer
11.1.2.2
Custom Design With WEBENCH® Tools
11.2
ドキュメントの更新通知を受け取る方法
11.3
サポート・リソース
11.4
Trademarks
11.5
静電気放電に関する注意事項
11.6
用語集
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RVF|40
MPQF268C
サーマルパッド・メカニカル・データ
RVF|40
QFND333E
発注情報
jajsio4a_oa
1
特長
分割レールをサポート:PVIN:2.95V~
18V
、AVIN:2.95V~18V (スイッチングのために VDD5 に 4V を入力する場合)
5.5mΩ/1.8mΩ
の MOSFET を内蔵
選択可能な内部補償付きの平均電流モード制御
2×、3×、4× スタック可能で最大
40A
の電流共有、出力ごとに 1 つのアドレスをサポート
選択可能な出力:ピン・ストラップで 0.5V~5.5V、またはPMBus の VOUT_COMMAND を使用して 0.25V~5.5V
豊富な PMBus コマンド・セット、V
OUT
、I
OUT
、および内部ダイ温度のテレメトリを含む
内部 FB 分圧抵抗を使用する差動リモート・センス機能、T
J
が –40℃~+150℃の範囲内で V
OUT
誤差 1% 未満
PMBus による AVS およびマージニング機能
MSEL ピンによる PMBus デフォルト値のピン設定
225kHz~1.5MHz で 12 のスイッチング周波数を選択可能 (8 つのピン・ストラップ・オプション)
周波数同期入力 / 同期出力
プリバイアス出力をサポート
強結合インダクタをサポート
7mm × 5mm × 1.5mm、40 ピン QFN、
0.5mm ピッチ
WEBENCH®
Power Designer
により、TPS546A24A を使用するカスタム設計を作成