Timing and electrical characteristics of the PMBus interface specification can be found in the PMB Power Management Protocol Specification, Part 1, revision 1.3 available at http://pmbus.org. The TPS546A24A device supports both the 100-kHz, 400-kHz, and 1-MHz bus timing requirements.

The TPS546A24A uses clock stretching during PMBus communication, but only stretches the clock during specific bits of the transaction.

• The TPS546A24A does not stretch the clock during the address byte of any transaction.
• The TPS546A24A can stretch the clock between bit 0 of the command byte and its ACK response.
• The TPS546A24A stretches the clock after bit 0 of the read address of a read transaction.
• The TPS546A24A stretches the clock between bit 0 of the last byte of data and its ACK response
• The TPS546A24A can stretch the clock between bit 1 and bit zero of every fourth byte of data for blocks with more than four bytes of data.

Communication over the PMBus interface can either support the packet error checking (PEC) scheme or not. If the master supplies clock (CLK) pulses for the PEC byte, PEC is used. If the CLK pulses are not present before a STOP, the PEC is not used. If PEC will always be used, consider enabling Require PEC in Section 7.6.83 to configure the TPS546A24A to reject any write transaction that does not include CLK pulses for a PEC byte.

The device supports a subset of the commands in the PMBus 1.3 Power Management Protocol Specification. See Section 7.5.1 for more information

The TPS546A24A also supports the SMB_ALERT response protocol. The SMB_ALERT response protocol is a mechanism by which the TPS546A24A can alert the bus master that it has experienced an alert and has important information for the host. The host should process this event and simultaneously accesses all slaves on the bus that support the protocol through the alert response address. All slaves that are asserting SMB_ALERT should acknowledge this request with their PMBus Address. The host performs a modified receive byte operation to get the address of the slave. At this point, the master can use the PMBus status commands to query the slave that caused the alert. For more information on the SMBus alert response protocol, see the system management bus (SMBus) specification. Persistent faults associated with status registers other than Section 7.6.60 will reassert SMB_ALERT after responding to the host alert response address.

The TPS546A24A contains non-volatile memory that is used to store configuration settings and scale factors. The settings programmed into the device are not automatically saved into this non-volatile memory. The Section 7.6.7 command must be used to commit the current PMBus settings to non-volatile memory as device defaults. The settings that are capable of being stored in non-volatile memory are noted in their detailed descriptions.

All pin programmable values can be committed to non-volatile memory. The POR default selection between pin programmable values and non-volatile memory can be selected by the manufacturer specific Section 7.6.84 command.