Layout is critical for good power-supply design. Figure 7-9 shows the recommended PCB-layout configuration. A list of PCB layout considerations using these devices is listed as follows:

• As with any switching regulator, several power or signal paths exist that conduct fast switching voltages or currents. Minimize the loop area formed by these paths and their bypass connections.
• Bypass the PVIN pins to PGND with a low-impedance path. Place the input bypass capacitors of the power-stage as close as physically possible to the PVIN and PGND pins. Additionally, a high-frequency bypass capacitor in a 0402 package on the PVIN pins can help reduce switching spikes. This capacitor can be placed on the other side of the PCB directly underneath the device to keep a minimum loop.
• The VDD5 bypass capacitor carries a large switching current for the gate driver. Bypassing the VDD5 pin to AGND at the thermal pad with a low-impedance path is very critical to the stable operation of the TPS546A24S devices. Place the VDD5 high-frequency bypass capacitors as close as possible to the device pins, with a minimum return loop back to the Thermal Pad.
• The AVIN bypass capacitor must be placed close to the AVIN pin and provide a low-impedance path to PGND at the thermal pad. If AVIN is powered from PVIN for single supply operation, AVIN and PVIN must be seperated with a 10-µs R-C filter to reduce PVIN switching noise on AVIN.
• The BP1V5 bypass capacitor must be placed close to the BP1V5 pin and provide a low-impedance path to DRTN. DRTN must not be connected to any other pin or node. DRTN is internally connected to AGND and by external connection to System Ground. Connecting DRTN to PGND or AGND can introduce a ground loop and errant operation.
• Keep signal components local to the device, and place them as close as possible to the pins to which they are connected. These components include the VOSNS and GOSNS series resistors and differential filter capacitor as well as MSEL1, MSEL2, VSEL, and ADRSEL resistors. Those components can be terminated to AGND with a minimum return loop or bypassed to the copper area of a separate low-impedance analog ground (AGND) that is isolated from fast switching voltages and current paths and has single connection to PGND on the thermal pad through the AGND pin. For placement recommendations, see Figure 7-9.
• The PGND pin (pin 26) must be directly connected to the thermal pad of the device on the PCB, with a low-noise, low-impedance path.
• Minimize the SW copper area for best noise performance. Route sensitive traces away from the SW and BOOT pins as these nets contain fast switching voltages and lend easily to capacitive coupling.
• Snubber component placement is critical for effective ringing reduction. These components must be on the same layer as the TPS546A24S devices, and be kept as close as possible to the SW and PGND copper areas.
• Route the VOSNS and GOSNS lines from the output capacitor bank at the load back to the device pins as a tightly coupled differential pair. These traces must be kept away from switching or noisy areas which can add differential-mode noise.
• Use caution when routing of the SYNC, VSHARE, BCX_CLK, and BCX_DAT traces for stackable configurations. The SYNC trace carries a rail-to-rail signal and must be routed away from sensitive analog signals, including the VSHARE, VOSNS, and GOSNS signals. The VSHARE traces must also be kept away from fast switching voltages or currents formed by the PVIN, AVIN, SW, BOOT, and VDD5 pins.