JAJSP25 November 2023 TPS546A24S
PRODUCTION DATA
| CMD Address | 04h |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| Phased: | No |
| NVM Back-up: | No |
| Updates: | On-the-fly |
The PHASE command provides the ability to configure, control, and monitor individual phases. Each PHASE contains the Operating Memory and User Store and Default Store for each phase output. The phase selected by the PHASE command will be used for all subsequent phase-dependent commands. The phase configuration needs to be established before any phase-dependent command can be successfully executed.
In the TPS546A24S, each PHASE is a separate device. The loop and PMBus loop controller device, GOSNS/FLWR connected to ground, will always be PHASE = 00h. loop follower devices, GOSNS/FLWR connected to BP1V5, have their phase assignment defined by their phase position, as defined by INTERLEAVE or MSEL2
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW | RW | RW | RW | RW | RW | RW | RW |
| PHASE | |||||||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7:0 | PHASE | RW | FFh | 00h: All commands address Phase 1. 01h: All commands address Phase 2. 02h: All commands address Phase 3. 03h: All commands address Phase 4. 04h-FEh: Unsupported/Invalid data FFh: Commands are addressed to all phases as a single entity. See the following text for more information. |
The range of valid data for PHASE also depends on the phase configuration. Attempts to write (04h) PHASE to a value not supported by the current phase configuration will be considered invalid/unsupported data and cause the TPS546A24S to respond by flagging the appropriate status bits and notifying the host according to the PMBus 1.3.1 Part II specification, section 10.9.3.