JAJSFL9C July 2016 – June 2018 TPS546C20A
PRODUCTION DATA.
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The STEP_VREF_MARGIN_LOW command, specifying a negative offset voltage on EA_VREF, is used to decrease the reference voltage by shifting the reference lower. When the OPERATION command is set to Margin Low, the output will decrease by the voltage indicated by this command.
For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.
The effect of this command is determined by the settings of the VOUT_MODE command. In this device, the VOUT_MODE is fixed to Linear with an exponent of –9 (decimal). The actual reference voltage commanded by a margin low command can be found in Equation 14.
The margin low range is between -64*1.953 mV and -1*1.953 mV in 1.953-mV steps.
If a value outside this range is given with this command, the device sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.
The value of EA_REF including STEP_VREF_MARGIN_LOW is also limited by the values of VOUT_MAX, VOUT_MIN, VOUT_COMMAND, VOUT_SCALE_LOOP and VREF_TRIM. See VOUT_MAX and VOUT_MIN for additional details.
The EA_REF voltage transition occurs at the rate determined by the current state:
| COMMAND | STEP_VREF_MARGIN_LOW | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Format | Linear, two's complement binary | |||||||||||||||
| Bit Position | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Access | r/w | r | r | r | r | r | r | r | r | r | r/w | r/w | r/w | r/w | r/w | r/w |
| Function | High Byte | Low Byte | ||||||||||||||
High Byte:
default: 1111 1111 (binary) (MSB is sign bit, sign extended)
Low Byte:
Minimum: 1100 0000 (binary) –64 (decimal) (–125 mV)
Maximum: 1111 1111 (binary) –1 (decimal) (–2 mV)
The read-writeable bits in this register do NOT have direct EEPROM backup; however, the register does restore to one of two configurable values as determined by RSMLO_VAL in (E5h) MFR_SPECIFIC_21 (OPTIONS).