SLVSH95 July   2024 TPS546C25

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  D-CAP4 Control
        1. 6.3.1.1 Loop Compensation
      2. 6.3.2  Internal VCC LDO and Using an External Bias on VCC Pin and VDRV Pin
      3. 6.3.3  Input Undervoltage Lockout (UVLO)
        1. 6.3.3.1 Fixed VCC_OK UVLO
        2. 6.3.3.2 Fixed VDRV UVLO
        3. 6.3.3.3 Programmable PVIN UVLO
        4. 6.3.3.4 Control (CNTL)Enable
      4. 6.3.4  Differential Remote Sense and Internal, External Feedback Divider
      5. 6.3.5  Set the Output Voltage and VORST#
      6. 6.3.6  Start-Up and Shutdown
      7. 6.3.7  Dynamic Voltage Slew Rate
      8. 6.3.8  Set Switching Frequency
      9. 6.3.9  Switching Node (SW)
      10. 6.3.10 Overcurrent Limit and Low-side Current Sense
      11. 6.3.11 Negative Overcurrent Limit
      12. 6.3.12 Zero-Crossing Detection
      13. 6.3.13 Input Overvoltage Protection
      14. 6.3.14 Output Overvoltage and Undervoltage Protection
      15. 6.3.15 Overtemperature Protection
      16. 6.3.16 Telemetry
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 DCM Light Load Operation
      3. 6.4.3 Powering the Device From a 12V Bus
      4. 6.4.4 Powering the Device From a Split-rail Configuration
      5. 6.4.5 Pin Strapping
        1. 6.4.5.1 Programming MSEL1
        2. 6.4.5.2 Programming PMB_ADDR
        3. 6.4.5.3 Programming MSEL2
        4. 6.4.5.4 Programming VSEL\FB
    5. 6.5 Programming
      1. 6.5.1 Supported PMBus Commands
  8. 7 Register Maps
    1. 7.1  Conventions for Documenting Block Commands
    2. 7.2  (01h) OPERATION
    3. 7.3  (02h) ON_OFF_CONFIG
    4. 7.4  (03h) CLEAR_FAULTS
    5. 7.5  (04h) PHASE
    6. 7.6  (09h) P2_PLUS_WRITE
    7. 7.7  (0Ah) P2_PLUS_READ
    8. 7.8  (0Eh) PASSKEY
    9. 7.9  (10h) WRITE_PROTECT
    10. 7.10 (15h) STORE_USER_ALL
    11. 7.11 (16h) RESTORE_USER_ALL
    12. 7.12 (19h) CAPABILITY
    13. 7.13 (1Bh) SMBALERT_MASK
    14. 7.14 (20h) VOUT_MODE
    15. 7.15 (21h) VOUT_COMMAND
    16. 7.16 (22h) VOUT_TRIM
    17. 7.17 (24h) VOUT_MAX
    18. 7.18 (25h) VOUT_MARGIN_HIGH
    19. 7.19 (26h) VOUT_MARGIN_LOW
    20. 7.20 (27h) VOUT_TRANSITION_RATE
    21. 7.21 (29h) VOUT_SCALE_LOOP
    22. 7.22 (2Ah) VOUT_SCALE_MONITOR
    23. 7.23 (2Bh) VOUT_MIN
    24. 7.24 (33h) FREQUENCY_SWITCH
    25. 7.25 (35h) VIN_ON
    26. 7.26 (36h) VIN_OFF
    27. 7.27 (39h) IOUT_CAL_OFFSET
    28. 7.28 (40h) VOUT_OV_FAULT_LIMIT
    29. 7.29 (41h) VOUT_OV_FAULT_RESPONSE
    30. 7.30 (42h) VOUT_OV_WARN_LIMIT
    31. 7.31 (43h) VOUT_UV_WARN_LIMIT
    32. 7.32 (44h) VOUT_UV_FAULT_LIMIT
    33. 7.33 (45h) VOUT_UV_FAULT_RESPONSE
    34. 7.34 (46h) IOUT_OC_FAULT_LIMIT
    35. 7.35 (48h) IOUT_OC_LV_FAULT_LIMIT
    36. 7.36 (49h) IOUT_OC_LV_FAULT_RESPONSE
    37. 7.37 (4Ah) IOUT_OC_WARN_LIMIT
    38. 7.38 (4Fh) OT_FAULT_LIMIT
    39. 7.39 (50h) OT_FAULT_RESPONSE
    40. 7.40 (51h) OT_WARN_LIMIT
    41. 7.41 (55h) VIN_OV_FAULT_LIMIT
    42. 7.42 (60h) TON_DELAY
    43. 7.43 (61h) TON_RISE
    44. 7.44 (64h) TOFF_DELAY
    45. 7.45 (65h) TOFF_FALL
    46. 7.46 (78h) STATUS_BYTE
    47. 7.47 (79h) STATUS_WORD
    48. 7.48 (7Ah) STATUS_VOUT
    49. 7.49 (7Bh) STATUS_IOUT
    50. 7.50 (7Ch) STATUS_INPUT
    51. 7.51 (7Dh) STATUS_TEMPERATURE
    52. 7.52 (7Eh) STATUS_CML
    53. 7.53 (7Fh) STATUS_OTHER
    54. 7.54 (80h) STATUS_MFR_SPECIFIC
    55. 7.55 (88h) READ_VIN
    56. 7.56 (8Bh) READ_VOUT
    57. 7.57 (8Ch) READ_IOUT
    58. 7.58 (8Dh) READ_TEMPERATURE_1
    59. 7.59 (98h) PMBUS_REVISION
    60. 7.60 (99h) MFR_ID
    61. 7.61 (9Ah) MFR_MODEL
    62. 7.62 (9Bh) MFR_REVISION
    63. 7.63 (ADh) IC_DEVICE_ID
    64. 7.64 (AEh) IC_DEVICE_REV
    65. 7.65 (D1h) SYS_CFG_USER1
    66. 7.66 (D2h) PMBUS_ADDR
    67. 7.67 (D4h) COMP
    68. 7.68 (D5h) VBOOT_OFFSET_1
    69. 7.69 (D6h) STACK_CONFIG
    70. 7.70 (D8h) PIN_DETECT_OVERRIDE
    71. 7.71 (D9h) NVM_CHECKSUM
    72. 7.72 (DAh) READ_TELEMETRY
    73. 7.73 (79h) STATUS_ALL
    74. 7.74 (DDh) EXT_WRITE_PROTECTION
    75. 7.75 (A4h) IMON_CAL
    76. 7.76 (FCh) FUSION_ID0
    77. 7.77 (FDh) FUSION_ID1
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Input Capacitor Selection
        2. 8.2.3.2 Inductor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 Compensation Selection
        5. 8.2.3.5 VCC and VRDV Bypass Capacitors
        6. 8.2.3.6 BOOT Capacitor Selection
        7. 8.2.3.7 VOSNS and GOSNS Capacitor Selection
        8. 8.2.3.8 PMBus Address Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS546C25EVM
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

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発注情報

5.5 Electrical Characteristics

TJ = –40°C to +125°C. PVIN = 4V to 18V, VVCC = 4.5V to 5.0V (unless otherwise noted). Typical values are at TJ = 25°C, PVIN = 12V and VVCC = 4.5V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ(PVIN) PVIN quiescent current  Non-switching, PVIN = 12V, VCTRL = 0V, no external bias on VCC/VDRV pin 10 mA
ISD(PVIN) PVIN shutdown supply current PVIN = 12V, VEN = 0V, no bias on VCC and VDRV pins 20 µA
IVCC VCC external bias current 5V external bias on VCC+VDRV, regular switching. TJ = 25°C, PVIN = 12V, VOUT = 1.1V, VEN = 2V, fSW = 1MHz fSW = 1MHz 10 mA
fSW = 2MHz 10 mA
IVDRV VDRV external bias current 5V external bias on VCC+VDRV, regular switching. TJ = 25°C, PVIN = 12V, VOUT = 1.1V, VEN = 2V, fSW = 2MHz fSW = 1MHz 80 mA
fSW = 2MHz 80 mA
IQ(VDRV) VCC+VDRV quiescent current 5V external bias on VCC+VDRV, non-switching. PVIN = 12V, VEN = 0V 5 mA
INPUT UVLO AND OV
PVINOV PVIN overvoltage threshold (55h) VIN_OV_FAULT_LIMIT (55h) VIN_OV_FAULT_LIMIT = 16.5V 15.9 16.5 V
(55h) VIN_OV_FAULT_LIMIT = 18V 18.9 19.5 V
PVINOV PVIN overvoltage falling threshold.  PVIN_OVF status bit, once it is set, cannot be cleared unless PVIN falls below this threshold. PVIN falling
 13.5 V
VIN_ON PVIN turn-on voltage (35h) VIN_ON PVIN rising (35h) VIN_ON = 10V 10 V
(35h) VIN_ON = 9V 9 V
(35h) VIN_ON = 8V 8 V
VIN_ON (35h) VIN_ON = 7V 7 V
(35h) VIN_ON = 6V 6 V
(35h) VIN_ON = 5V 5 V
(35h) VIN_ON = 3.8V 3.8 V
(35h) VIN_ON = 2.5V 2.5 V
VIN_OFF PVIN turn-off voltage (36h) VIN_OFF PVIN falling (36h) VIN_OFF = 9.5V 9.5 V
(36h) VIN_OFF = 8.5V 8.5 V
(36h) VIN_OFF = 7.5V 7.5 V
(36h) VIN_OFF = 6.5V 6.5 V
(36h) VIN_OFF = 5.5V 5.5 V
(36h) VIN_OFF = 4.2V 4.2 V
(36h) VIN_OFF = 3.6V 3.6 V
VIN_OFF PVIN turn-off voltage (36h) VIN_OFF PVIN falling (36h) VIN_OFF = 2.3V 2.3 V
TDGLTCH(ON) VIN_ON deglitch time 50 µs
TDGLTCH(OFF) VIN_OFF deglitch time 5 µs
ENABLE
VEN(R) CTRL voltage rising threshold CTRL rising, enable switching 1.2 1.3 V
VEN(F) CTRL voltage falling threshold CTRL falling, disable switching 0.9 1.0 V
VEN(H) CTRL voltage hysteresis 0.2 V
tEN(DGLTCH) CTRL deglitch time (1) 0.2 µs
REN(PD) CTRL internal pulldown resistor (CTRL to AGND) VEN = 2V, CTRL pin to AGND 110 125 140 kΩ
INTERNAL VCC LDO
VVCC(LDO) Internal VCC LDO output voltage PVIN = 4V, IVCC(load) = 5mA PVIN = 4V, IVCC(load) = 5mA 3.925 3.97 4.0 V
VVCC(LDO) Internal VCC LDO output voltage PVIN = 5V to 18V, IVCC(load) = 5mA 4.28 4.44 4.55 V
VVCC(ON) VCC UVLO rising threshold VCC rising 3.74 3.80 3.86 V
VVCC(OFF) VCC UVLO falling threshold VCC falling  3.53 3.59 3.65 V
VVCC(DO) VCC LDO dropout voltage PVIN – VVCC, PVIN = 4V, IVCC(load) = 45mA 90 144 226 mV
IVCC(SC) VCC LDO short-circuit current limit PVIN = 12V 150 200 mA
VOUT VOLTAGE
VOUT(ACC) Output voltage regulation accuracy TJ = 0°C to 85°C VOUT = 0.5V, VOSL = 1, VVOSNS–VGOSNS 0.495 0.5 0.505 V
VOUT = 1V, VOSL = 0.5, VVOSNS–VGOSNS 0.995 1 1.005 V

VOUT = 1.8V, VOSL = 0.25, VVOSNS–VGOSNS
 		 1.791 1.8 1.809 V

VOUT = 3.3V, VOSL = 0.125, VVOSNS–VGOSNS
 		 3.284 3.3 3.316 V
TJ = –40°C to 125°C
VOUT = 0.5V, VOSL = 1, VVOSNS–VGOSNS
 		 0.4925 0.5 0.5075 V

VOUT = 1V, VOSL = 0.5, VVOSNS–VGOSNS
 		 0.990 1 1.01 V

VOUT = 1.8V, VOSL = 0.25, VVOSNS–VGOSNS
 		 1.782 1.8 1.818 V

VOUT = 3.3V, VOSL = 0.125, VVOSNS–VGOSNS
 		 3.267 3.3 3.333 V
IVOS VOSNS input current VVOSNS = 1.8V, VOSL = 0.25 60 100 µA
VOUTRES Resolution of VOUT_COMMAND and VOUT_TRIM 1.953 mV
VOSL VOUT_SCALE_LOOP. Internal feedback loop scaling factor. Programmable range, 4 discrete settings 0.125 1
VOUT_TRIM Programmable range -125 123 mV
VOUT_TR Output voltage transition rate accuracy VOUT_TRANSITION_RATE = 10mV/µs 8.8 9.77 10.7 mV/µs
SWITCHING FREQUENCY
fSW(FCCM) Switching frequency (33h) FREQUENCY_SWITCH PVIN = 12V, FCCM, VOUT = 1.1V, no load (33h) FREQUENCY_SWITCH = 000b 400 440 kHz
(33h) FREQUENCY_SWITCH = 001b 510 600 660 kHz
(33h) FREQUENCY_SWITCH = 010b 680 800 920 kHz
(33h) FREQUENCY_SWITCH = 011b 850 1000 1150 kHz
(33h) FREQUENCY_SWITCH = 100b 1020 1200 1440 kHz
(33h) FREQUENCY_SWITCH = 101b 1400 kHz
(33h) FREQUENCY_SWITCH = 110b 1800 kHz
(33h) FREQUENCY_SWITCH = 111b 2000 kHz
STARTUP AND SHUTDOWN TIMING
tON(DLY) Power on sequence delay, (60h) TON_DELAY VVCC = 4.5V TON_DELAY = 0ms 0.05 0.1 ms
TON_DELAY = 0.5ms 0.5 0.55 ms
TON_DELAY = 1.0ms 1.0 1.1 ms
TON_DELAY = 2.0ms 2.0 2.2 ms
tON(Rise) Soft-start time, (61h) TON_RISE VVCC = 4.5V TON_RISE = 0.5ms 0.5 0.55 ms
TON_RISE = 1.0ms 1.0 1.1 ms
TON_RISE = 2.0ms 2.0 2.2 ms
TON_RISE = 4.0ms 4.0 4.4 ms
TON_RISE = 8.0ms 8.0 8.8 ms
TON_RISE = 16.0ms 16.0 17.6 ms
tOFF(DLY) Power off sequence delay, (64h) TOFF_DELAY VVCC = 4.5V TOFF_DELAY = 0ms 0 0.05 ms
TOFF_DELAY = 1.0ms 1.0 1.1 ms
TOFF_DELAY = 1.5ms 1.5 1.65 ms
TOFF_DELAY = 2.0ms 2.0 2.2 ms
SR(Fall) Soft-stop slew rate, (65h) TOFF_FALL VVCC = 4.5V, VOSL = 0.5 or 5mV VID table, VDACBOOT = 0.55V TOFF_FALL = 0.5ms -2.22 mV/µs
TOFF_FALL = 1ms -1.11 mV/µs
TOFF_FALL = 2ms -0.56 mV/µs
TOFF_FALL = 4ms -0.28 mV/µs
VVCC = 4.5V, VOSL = 0.25 or 10mV VID table, VDACBOOT = 0.45V TOFF_FALL = 0.5ms -3.64 mV/µs
TOFF_FALL = 1ms -1.82 mV/µs
TOFF_FALL = 2ms -0.91 mV/µs
TOFF_FALL = 4ms -0.46 mV/µs
POWER STAGE
RDSON(HS) High-side MOSFET on-resistance TJ = 25°C, PVIN = 12V, VBOOT-SW = 4.5V 3.3 mΩ
TJ = 25°C, PVIN = 12V, VBOOT-SW = 5V 3.18 mΩ
RDSON(LS) Low-side MOSFET on-resistance TJ = 25°C, PVIN = 12V, VVCC/VDRV = 4.5V 1 mΩ
TJ = 25°C, PVIN = 12V, VVCC/VDRV = 5V 0.96 mΩ
tON(min) Minimum ON pulse width VVCC/VDRV = 4.5V 30 ns
tOFF(min) Minimum OFF pulse width VVCC/VDRV = 4.5V, IO =1.5A, VOUT = VOUT(set) – 20mV, SW falling edge to rising edge 210 ns
BOOTSTRAP CIRCUIT
IBOOT(LKG) BOOT leakage current VEN = 2V, VBOOT-SW = 5V 150 µA
VBT-SW(UV_F) BOOT-SW UVLO falling threshold 3 V
OVERCURRENT PROTECTION
ILS(OC) Low-side MOSFET valley overcurrent limit, (46h) IOUT_OC_FAULT_LIMIT IOUT_OC_FAULT_LIMIT = 10A 8.5 10 11.5 A
IOUT_OC_FAULT_LIMIT = 12A TBD 12 TBD A
IOUT_OC_FAULT_LIMIT = 15A 13.5 15 16.5 A
IOUT_OC_FAULT_LIMIT = 16A TBD 19 TBD A
IOUT_OC_FAULT_LIMIT = 20A TBD 21 TBD A
IOUT_OC_FAULT_LIMIT = 24A TBD 24 TBD A
IOUT_OC_FAULT_LIMIT = 25A TBD 28 TBD A
IOUT_OC_FAULT_LIMIT = 30A 27 30 33 A
IOUT_OC_FAULT_LIMIT = 32A TBD 32 TBD A
IOUT_OC_FAULT_LIMIT = 35A 31.5 35 38.5 A
IOUT_OC_FAULT_LIMIT = 39A TBD 39 TBD A
IOUT_OC_FAULT_LIMIT = 40A 36 40 44 A
I(OCW) Average output current warning, (4Ah) IOUT_OC_WARN_LIMIT IOUT_OC_WARN_LIMIT = 5A TBD 5 TBD A
IOUT_OC_WARN_LIMIT = 10A 8.5 10 11.5 A
IOUT_OC_WARN_LIMIT = 15A 13.5 15 16.5 A
IOUT_OC_WARN_LIMIT = 20A 18 20 22 A
IOUT_OC_WARN_LIMIT = 25A 22.5 25 27.5 A
IOUT_OC_WARN_LIMIT = 30A 27 30 33 A
IOUT_OC_WARN_LIMIT = 35A 31.5 35 38.5 A
IOUT_OC_WARN_LIMIT = 40A 36 40 44 A
IOUT_OC_WARN_LIMIT = 45A 40.5 45 49.5 A
IOUT_OC_WARN_LIMIT = 50A 45 50 55 A
IOUT_OC_WARN_LIMIT = 55A 49.5 55 60.5 A
ILS(NOC) Low-side MOSFET negative overcurrent limit, SEL_UCF = 00b –28.8 –24 –19.2 A
SEL_UCF = 01b –24 –20 –16 A
SEL_UCF = 10b –20 –16 –12 A
SEL_UCF = 11b –10.8 –8 –5.6 A
STACKING INTERFACE
VIH(TRIG) High-level Primary detection input voltage Secondary device TRIG input to determine rimary device synchronization 2.5 3.2 V
VIL(sync) Low-level input voltage triggering Secondaty device TRIG input to determine triggering 1.85 2.3 V
VOHH(TRIG) TRIG output high voltage for Primary synchronization 2.5 3.2 V
Minimum pulse width detection of TRIG pulse Secondary device input 10 ns
Minimum pulse width of TRIG pulse Primary device output 25 ns
CURRENT SHARING
ISHARE(acc) Output current sharing accuracy of two devices defined as the ratio of the current difference between two devices to the sum of the two IOUT ≥ 20A per device –10% +10%
%
VISHARE fault trip threshold V
ISHARE(acc) Output current sharing accuracy of two devices defined as the current difference between each device and the average of all devices IOUT < 20A per device –2 2 A
VISHARE fault release threshold V
OUTPUT OVF/UVF
VOVF Vout overvoltage fault (OVF) threshold, (40h) VOUT_OV_FAULT_LIMIT (VOSNS –  GOSNS) rising VOUT_OV_FAULT_LIMIT = 573d 112% VOC
VOUT_OV_FAULT_LIMIT = 594d 116% VOC
VOUT_OV_FAULT_LIMIT = 614d 120% VOC
VOUT_OV_FAULT_LIMIT = 717d 150% VOC
VOVF(acc) Vout OVF accuracy (VOSNS –  GOSNS) rising –3% 3% VOC
VUVF Vout undervoltage fault (UVF) threshold, (44h) VOUT_UV_FAULT_LIMIT (VOSNS –  GOSNS) falling VOUT_UV_FAULT_LIMIT = 430d 84% VOC
VOUT_UV_FAULT_LIMIT = 389d 76% VOC
VOUT_UV_FAULT_LIMIT = 348d 68% VOC
VOUT_UV_FAULT_LIMIT = 307d 60% VOC
VOVF(acc) Vout UVF accuracy (VOSNS –  GOSNS) falling –3% 3% VOC
Vout UVF and UVW delay time (45h) VOUT_UV_FAULT_RESPONSE<2:0> = x00b 2 µs
(45h) VOUT_UV_FAULT_RESPONSE<2:0> = x01b 16 µs
(45h) VOUT_UV_FAULT_RESPONSE<2:0> = x10b 64 µs
(45h) VOUT_UV_FAULT_RESPONSE<2:0> = x11b 256 µs
THICCUP Hiccup sleep time before a restart. Applicable to all faults with hiccup response option. (45h) VOUT_UV_FAULT_RESPONSE<5:3> = 111b 52 ms
VOVF(FIX) VOUT fixed OVF protection threshold
VOUT_SCALE_LOOP = 1

 OVF_FIXED = 0b 0.75 V
OVF_FIXED = 1b 0.9 V
VOUT_SCALE_LOOP = 0.5 OVF_FIXED = 0b 1.425 1.5 1.575 V
OVF_FIXED = 1b 1.71 1.8 1.89 V
VOUT_SCALE_LOOP = 0.25 OVF_FIXED = 0b 2.93 3.0 3.07 V
OVF_FIXED = 1b 3.6 V
VOUT_SCALE_LOOP = 0.125 OVF_FIXED = 0b 4.8 V
OVF_FIXED = 1b 6.0 V
OUTPUT OVW/UVW
VOVW Overvoltage warning (OVW) threshold, (42h) VOUT_OV_WARN_LIMIT (VOSNS – GOSNS) rising VOUT_OV_WARN_LIMIT = 553d 105% 108% 111% VOC
VOUT_OV_WARN_LIMIT = 573d 112% VOC
VOUT_OV_WARN_LIMIT = 594d 116% VOC
VOUT_OV_WARN_LIMIT = 655d 128% VOC
tOVW(DLY) OVW delay time (VOSNS – GOSNS) > VOVW 2 µs
VUVW(range) Undervoltage warning (UVW) threshold, (43h) VOUT_UV_WARN_LIMIT programmable range (VOSNS – GOSNS) falling 68% 96% VOC
VUVW(res) Undervoltage warning (UVW) threshold resolution 4% VOC
VUVW Undervoltage warning (UVW) threshold, (43h) VOUT_UV_WARN_LIMIT (VOSNS – GOSNS) falling VOUT_UV_WARN_LIMIT = 492d 96% VOC
VOUT_UV_WARN_LIMIT = 471d 89% 92% 95% VOC
VOUT_UV_WARN_LIMIT = 451d 88% VOC
VOUT_UV_WARN_LIMIT = 430d 84% VOC
POWER GOOD
tPG(DLY_RISE) PG rising edge delay (soft-start done to high delay time, only occurs during startup) PGD_DEL = 00b 0 ms
PGD_DEL = 01b 0.5 ms
PGD_DEL = 10b 1.0 ms
PGD_DEL = 11b 2.0 ms
tPG(DLY_UVF) PG falling edge UVF delay 1 µs
PG sink current VPG = 0.3V, VVCC = 4.5V 10 mA
IPG(LKG) PG pin leakage current when open drain output is high VPG = 5V 5 µA
VOL(PG) PG pin output low-level voltage IPG = 10mA, VIN = 12V, VVCC = 4.5V 300 mV
Minimum VCC for valid PG output VEN = 0V, Rpullup = 10kΩ VPG ≤ 0.3V 1.2 V
RESET (VORST#)
VTH_H(reset) High-level voltage threshold (1.8V logic) (PMBus only) VORST# pin SEL_VORST_TH = 1 1.1 1.35 V
VTH_L(reset) Low-level voltage threshold (1.8V logic) (PMBus only) VORST# pin SEL_VORST_TH = 1 0.8 0.9 V
VHYS(reset) Input voltage hysteresis (1.8V logic) (PMBus only) VORST# pin SEL_VORST_TH = 1 TBD V
VTH_H(reset) High-level voltage threshold (1.2V logic) (All) VORST# pin SEL_VORST_TH = 0 0.6 0.65 V
VTH_L(reset) Low-level voltage threshold (1.2V logic) (All) VORST# pin SEL_VORST_TH = 0 0.45 0.5 V
VHYS(reset) Input voltage hysteresis (1.2V logic) (All) VORST# pin SEL_VORST_TH = 0 TBD V
VIH(reset) Input logic low (1.8V logic) VORST# pin SEL_VORST_TH = 1 0.8 V
VIL(reset) Input logic high (1.8V logic) VORST# pin SEL_VORST_TH = 1 1.35 V
VIH(reset) Input logic low (1.2V logic) VORST# pin SEL_VORST_TH = 0 0.4 V
VIL(reset) Input logic high (1.2V logic) VORST# pin SEL_VORST_TH = 0 0.9 V
tPW(reset) Minimum VORST# pulse-width (1) 0.2 µs
THERMAL SHUTDOWN AND TEMPERATURE PROTECTION
TJ(SD) Thermal shutdown threshold (1) Junction temperature rising 153 166 °C
TJ(HYS) Thermal shutdown hysteresis (1) 30
TOT(FAULT) Over temperature fault threshold, (4Fh) OT_FAULT_LIMIT Programmable range 125 165
Resolution 10
TOT(WARN) Over temperature warning threshold, (51h) OT_WARN_LIMIT Programmable range 95 130
Resolution 5
TELEMETRY (PMBUS)
MIOUT(rng) Output current measurement range 0 45.7 A
MIOUT(acc) Output current measurement accuracy datapoints 0-125°C IOUT = 4A 2.5 4 5.5 A
IOUT = 12A 10.5 12 13.5 A
IOUT = 24A 22.1 24 25.92 A
IOUT = 40A 36.8 40 43.2 A
Output current measurement accuracy 0A ≤ IOUT ≤ 12A −1.5 1.5 A
IOUT = 15A −10% 10%
24A < IOUT ≤ 40A −8% 8%
MVOUT(rng) Output voltage measurement range 0 6 V
MVOUT(acc) Output voltage measurement accuracy datapoint VOUT_SCALE_LOOP = 1 VOUT = 0.5V 0.49 0.5 0.51 V
VOUT_SCALE_LOOP = 0.5 VOUT = 0.75V 0.737 0.75 0.763 V
VOUT_SCALE_LOOP = 0.5 VOUT = 1.1V 1.087 1.1 1.113 V
VOUT_SCALE_LOOP = 0.25 VOUT = 1.5V 1.481 1.5 1.519 V
VOUT_SCALE_LOOP = 0.25 VOUT = 1.8V 1.775 1.8 1.825 V
VOUT_SCALE_LOOP = 0.125 VOUT = 3.3V 3.234 3.3 3.366 V
MPVIN(rng) Input voltage measurement range 4 18 V
MPVIN(acc) Input voltage measurement accuracy datapoint TJ = 25°C VIN = 8V 8 V
VIN = 12V 11.9 12 12.1 V
VIN = 16V 16 V
MTSNS(rng) Internal temperature sense range −40 150 °C
MTSNS(acc) Internal temperature sense accuracy –40°C ≤ TJ ≤ 150°C −4 4 °C
PMBUS INTERFACE
VIH(PMBUS) High-level input voltage on PMB_CLK, PMB_DATA 1.35 V
VIL(PMBUS) Low-level input voltage on PMB_CLK, PMB_DATA 0.8
IlH(PMBUS) Input high level current into PMB_CLK, PMB_DATA –10 10 µA
VOL(PMBUS) Output low level voltage on PMB_DATA and SMB_ALERT#/PINALRT#/CAT_FAULT# VCC ≥ 4.5V, Ipin = 20mA 0.4 V
IOH(PMBUS) Output high level open drain leakage current into PMB_DATA, SMB_ALERT#/PINALRT#/CAT_FAULT# Vpin = 5.5V 10 µA
IOL(PMBUS) Output low level open drain sinking current on PMB_DATA, SMB_ALERT#/PINALRT#/CAT_FAULT# Vpin = 0.4V 20 mA
CPIN_PMB PMB_CLK and PMB_DATA pin input capactiance (1) Vpin = 0.1V to 1.35V 5 pF
fPMBUS_CLK PMBus operating frequency range 10 1000 kHz
tBUF Bus free time between a STOP and START condition 0.5 µs
tHD_STA Hold time for a (repeated) START condition 0.26 µs
tSU_STA Setup time for a repeated START condition 0.26 µs
tSU_STO Setup time for a STOP condition 0.26 µs
tHD_PMB PMB_DATA hold time 0 µs
tSU_PMB PMB_DATA setup time 50 ns
tTIMEOUT Detect clock low timeout 25 30 35 ms
tLOW Low period of PMB_CLK 0.5 µs
tHIGH High period of PMB_CLK 0.26 µs
tR_PMB PMB_CLK and PMB_DATA rise time (1) 1000kHz class; VIL(MAX) - 150mV to VIH(MIN) + 150mV 120 ns
tF_PMB PMB_CLK and PMB_DATA fall time (1) 1000kHz class; VIH(MIN) + 150mV to VIL(MAX) - 150mV 120 ns
NWR_NVM Number of NVM writeable cycles (1) –40°C ≤ TJ ≤ 125°C 1000 cycle
(1) Specified by design