JAJSQT1 July 2024 TPS546E25
ADVANCE INFORMATION
| CMD Address | D1h |
| Write Transaction: | Write Word |
| Read Transaction: | Read Word |
| Format: | Unsigned Binary (2 bytes) |
| NVM Back-up: | EEPROM |
| Updates: | On-the-fly |
This command contains miscellaneious bits for system configuration.
Return to Supported PMBus Commands.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| FCCM | 0 | EN_SS_DCM | PGD_DEL | SEL_UCF | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| PEC_REQ | 0 | 0 | EXT_DIV | SEL_HI_VORST_TH | EN_VORST | SEL_FIX_OVF | EN_FIX_OVF |
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 15 | FCCM | R/W | NVM | Forced CCM operation. 1b: Forces continuous conduction in the switching converter. 0b: DCM operation is enabled and automatically entered/exited based on zero-crossing detection of the LFET sensed current. The bit is updated when disabled. PMBus writes are always accepted and the data is updated; however, in order for this bit to take effect, the rail must be disabled. When in stacked configuration, FCCM is always set to 1b. |
| 14:13 | 0 | R/W | 00b | Not supported and always 0. |
| 12 | EN__SS_DCM | R/W | NVM | Enable DCM during SS (soft start). 1b: DCM operation is enabled during soft start. This will override the setting in the FCCM bit during soft start. 0b: DCM operation is disabled during soft start. |
| 11:10 | PGD_DEL | R/W | NVM | PG delay. These bits indicate the rising edge deglitch time from SS_DONE going
high to PGOOD pin going high. As a result, this deglitch time is included only once
per startup of the rail. PMBus writes are always accepted and the data is updated;
however, in order for this bit to take effect, the rail must be disabled. 00b: 0.0015ms delay. 01b: 0.5ms delay. 10b: 1ms delay. 11b: 2ms delay. |
| 9:8 | SEL_UCF | R/W | NVM | These bits select the UCF threshold. |
| 7 | PEC_REQ | R/W | NVM | Require Packet Error Check (PEC) on all transactions. If not
primary, this bit will be ignored. 0b: Respond to PEC per normal. Accept commands when no PEC is provided. Process PEC when additional PEC byte provided 1b: Reject any command transaction received without PEC. Respond as though an invalid PEC byte had been received. |
| 6:5 | 0 | R/W | 00b | Not supported and always 0. |
| 4 | EXT_DIV | R/W | NVM | Select external divider resistor. This bit is used to provide status on the selection of an external divider resistor versus an internal divider. This bit is set via pinstrap. Writes are accepted but are not stored. Reads will return pinstrapped value. |
| 3 | SEL_HI_VORST_TH | R/W | NVM | Select high threshold for VORST. 0b: VORST threshold is VH=0.6V, VL=0.5V 1b:VORST threshold is VH=1.1V, VL=0.9V |
| 2 | EN_VORST | R/W | NVM | Enable VOUT reset (VORST). 0b: Pulling down on (PMB_ADDR/VORST) has no effect on regulated output voltage; Vout remains unchanged 1b:Pulling down on (PMB_ADDR/VORST) has the effect of changing the regulated output voltage to VBOOT at a slew-rate specified by (27h) VOUT_TRANSITION_RATE. The transition to VBOOT will occur if the VORST# pin is low at the time of setting EN_VORST to 1. |
| 1 | SEL_FIX_OVF | R/W | NVM | Fixed OVF threshold selection. 0b: OVF threhold is 0.75V when (29h) VOUT_SCALE_LOOP mantissa is 8 0b: OVF threhold is 1.5V when (29h) VOUT_SCALE_LOOP mantissa is 4 0b: OVF threhold is 3.0V when (29h) VOUT_SCALE_LOOP mantissa is 2 0b: OVF threhold is 4.8V when (29h) VOUT_SCALE_LOOP mantissa is 1 1b: OVF threhold is 0.9V when (29h) VOUT_SCALE_LOOP mantissa is 8 1b: OVF threhold is 1.8V when (29h) VOUT_SCALE_LOOP mantissa is 4 1b: OVF threhold is 3.6V when (29h) VOUT_SCALE_LOOP mantissa is 2 1b: OVF threhold is 6.0V when (29h) VOUT_SCALE_LOOP mantissa is 1 |
| 0 | EN_FIX_OVF | R/W | NVM | Fixed OV fault. 0b: Fixed OVF enabled. 1b: Fixed OVF disabled. |