JAJSSB2 September   2024 TPS548B23

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  D-CAP4 Control
      2. 7.3.2  Internal VCC LDO and Using External Bias On the VCC Pin
        1. 7.3.2.1 Powering the Device From a Single Bus
        2. 7.3.2.2 Powering the Device From a Split-Rail Configuration
      3. 7.3.3  Multifunction Configuration (CFG1-5) Pins
        1. 7.3.3.1 Multifunction Configuration (CFG1-2) Pins (Internal Feedback)
        2. 7.3.3.2 Multifunction Configuration (CFG1-2) Pins (External Feedback)
        3. 7.3.3.3 Multifunction Configuration (CFG3-5) Pins
      4. 7.3.4  Enable
      5. 7.3.5  Soft Start
      6. 7.3.6  Power Good
      7. 7.3.7  Overvoltage and Undervoltage Protection
      8. 7.3.8  Remote Sense
      9. 7.3.9  Low-side MOSFET Zero-Crossing
      10. 7.3.10 Current Sense and Positive Overcurrent Protection
      11. 7.3.11 Low-side MOSFET Negative Current Limit
      12. 7.3.12 Output Voltage Discharge
      13. 7.3.13 UVLO Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip (PFM) Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Setting Point
        2. 8.2.2.2 Choose the Switching Frequency
        3. 8.2.2.3 Choose the Inductor
        4. 8.2.2.4 Choose the Output Capacitor
        5. 8.2.2.5 Choose the Input Capacitors (CIN)
        6. 8.2.2.6 VCC Bypass Capacitor
        7. 8.2.2.7 BOOT Capacitor
        8. 8.2.2.8 PG Pullup Resistor
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • VAN|19
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

TPS548B23 VAN Package, 19-Pin, 3mm × 3mm (0.4mm Pin Pitch) WQFN-HR (Top View)Figure 5-1 VAN Package, 19-Pin, 3mm × 3mm (0.4mm Pin Pitch) WQFN-HR (Top View)
TPS548B23 VAN Package, 19-Pin, 3mm × 3mm (0.4mm Pin Pitch) WQFN-HR (Bottom View)Figure 5-2 VAN Package, 19-Pin, 3mm × 3mm (0.4mm Pin Pitch) WQFN-HR (Bottom View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO
PG 1 O Open-drain power-good status signal. Connect an external pullup resistor to a voltage source. When the FB voltage moves outside the specified limits, PG goes low after the specified delay.
CFG2 2 I Multi-function select pin. Connection to AGND, VCC, or floating this pin selects between the operating frequency, and the overcurrent limit. When configured for external FB operation, connecting a resistor between this pin and AGND sets the OCP limit.
CFG1 3 I Multi-function select pin. Connection to AGND, VCC, or floating this pin selects between the operating frequency, and the over current limit. When configured for external FB operation, connecting a resistor between this pin and AGND selects switching frequency, SS time, and fault recovery (hiccup or latch-off) mode.
VIN 4, 12 P Power-supply input pins for both the power stage MOSFETs and the internal LDO. Place the decoupling input capacitors from VIN pins to PGND pins as close as possible. A capacitor from each VIN to PGND close to IC is required.
PGND 5, 11 G Ground return for the power stage. This pin is internally connected to the source of the low-side MOSFET. Place as many vias as possible beneath the PGND pins and as close as possible to the PGND pins. This action minimizes parasitic impedance and also lowers thermal resistance.
VCC 6 P Internal 3V LDO output. A 3.3V or 5V external bias can be connected to this pin to save the power losses on the internal LDO. The voltage source on this pin powers both the internal circuitry and gate driver. Bypass with a 1μF, > 6.3V rating, ceramic capacitor from VCC pin to PGND. Place this capacitor as close to the VCC and PGND pins as possible.
SW 7, 8, 9 O Output switching terminal of the power converter. Connect this pin to the output inductor.
BST 10 I/O Supply for the internal high-side MOSFET gate driver (boost terminal). Connect the bootstrap capacitor from this pin to SW node.
CFG3 13 I Multi-function select pins. Connection CFGx to AGND, VCC, or floating this pin selects the output voltage setting/configuration (internal or external FB) and forced continuous conduction mode (FCCM) or skip-mode operation, .
CFG4 14 I
CFG5 15 I
EN 16 I Enable pin. The enable pin turns the DC/DC switching converter on or off. Floating EN pin before start-up disables the converter. The recommended maximum voltage applied to the EN pin is 5.5V. TI does not recommend connecting the EN pin to VIN pin directly.
VOS/FB 17 I Output voltage feedback input. Positive input of the differential remote sense circuit, connect to the Vout sense point on the load side. When configured for external feedback, a resistor divider from the VOUT to GOS (tapped to FB pin) sets the output voltage.
GOS 18 I Negative input of the differential remote sense circuit. Connect to a ground sense point near the load.
AGND 19 G Analog ground return and reference for the internal control circuits.
(1) I = Input, O = Output, P = Supply, G = Ground