JAJSSB2 September   2024 TPS548B23

ADVANCE INFORMATION  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  D-CAP4 Control
      2. 7.3.2  Internal VCC LDO and Using External Bias On the VCC Pin
        1. 7.3.2.1 Powering the Device From a Single Bus
        2. 7.3.2.2 Powering the Device From a Split-Rail Configuration
      3. 7.3.3  Multifunction Configuration (CFG1-5) Pins
        1. 7.3.3.1 Multifunction Configuration (CFG1-2) Pins (Internal Feedback)
        2. 7.3.3.2 Multifunction Configuration (CFG1-2) Pins (External Feedback)
        3. 7.3.3.3 Multifunction Configuration (CFG3-5) Pins
      4. 7.3.4  Enable
      5. 7.3.5  Soft Start
      6. 7.3.6  Power Good
      7. 7.3.7  Overvoltage and Undervoltage Protection
      8. 7.3.8  Remote Sense
      9. 7.3.9  Low-side MOSFET Zero-Crossing
      10. 7.3.10 Current Sense and Positive Overcurrent Protection
      11. 7.3.11 Low-side MOSFET Negative Current Limit
      12. 7.3.12 Output Voltage Discharge
      13. 7.3.13 UVLO Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip (PFM) Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Setting Point
        2. 8.2.2.2 Choose the Switching Frequency
        3. 8.2.2.3 Choose the Inductor
        4. 8.2.2.4 Choose the Output Capacitor
        5. 8.2.2.5 Choose the Input Capacitors (CIN)
        6. 8.2.2.6 VCC Bypass Capacitor
        7. 8.2.2.7 BOOT Capacitor
        8. 8.2.2.8 PG Pullup Resistor
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
  • VAN|19
サーマルパッド・メカニカル・データ
発注情報

Choose the Output Capacitor

There are three considerations for selecting the value of the output capacitor:

  1. Stability
  2. Steady state output voltage ripple
  3. Regulator transient response to a change load current
First, calculate the minimum output capacitance based on these three requirements. Equation 13 calculates the minimum capacitance to keep the LC double pole below 1/30th the fSW to meet stability requirements. This requirement helps to keep the LC double pole close to the internal zero. Equation 14 calculates the minimum capacitance to meet the steady state output voltage ripple requirement of 16mV. These calculations are for CCM operation and does not include the portion of the output voltage ripple caused by the ESR or ESL of the output capacitors.

Equation 13. C O U T _ S T A B I L I T Y > 30 2 π × f S W 2 × 1 L = 30 2 π × 800 k H z 2 × 1 0.55 μ H = 64.8 μ F
Equation 14. C O U T _ R I P P L E > I R I P P L E 8 × V R I P P L E × f S W = 5.95 A 8 × 16 m V × 800 k H z = 58.1 μ F

Equation 16 and Equation 17 calculate the minimum capacitance to meet the transient response requirement of 99mV with a 10A step. These equations calculate the necessary output capacitance to hold the output voltage steady while the inductor current ramps up or ramps down after a load step.

Equation 15. C O U T _ U N D E R S H O O T > L × I S T E P 2 × V O U T V I N m i n × f S W + t O F F _ M I N m a x 2 × V T R A N S × V O U T × V I N m i n - V O U T V I N m i n × f S W - t O F F _ M I N m a x
Equation 16. C O U T _ U N D E R S H O O T > 0.55 μ H × 10 A 2 × 3.3 V 8 V × 800 k H z + 150 n s 2 × 99 m V × 3.3 V × 8 V - 3.3 V 8 V × 800 k H z - 150 n s = 732 μ F
Equation 17. C O U T _ O V E R S H O O T > L × I S T E P 2 2 × V T R A N S × V O U T = 0.55 μ H × 10 A 2 2 × 99 m V × 3.3 V = 84.2 μ F

The output capacitance needed to meet the overshoot requirement is the highest value, so this sets the required minimum output capacitance for this example. Stability requirements can also limit the maximum output capacitance. Equation 18 calculates the recommended maximum output capacitance. This calculation keeps the LC double pole above 1/100th the fSW.

Equation 18. C O U T _ S T A B I L I T Y < 50 π × f S W 2 × 1 L = 50 π × 800 k H z 2 × 1 0.55 μ H = 720 μ F

Using more output capacitance is possible, but the stability must be checked through a bode plot or transient response measurement. The selected output capacitance is 6 × 47μF, 10V ceramic capacitors. When using ceramic capacitors, the capacitance must be derated due to DC and AC bias effects. The selected capacitors derate to 48% the nominal value giving an effective total capacitance of 135μF. This effective capacitance meets the minimum and maximum requirements.

This application uses all ceramic capacitors so the effects of ESR on the ripple and transient were ignored. If using non ceramic capacitors, as a starting point, the ESR must be below the values calculated in Equation 19 to meet the ripple requirement and Equation 20 to meet the transient requirement. For more accurate calculations or if using mixed output capacitors, the impedance of the output capacitors must be used to determine if the ripple and transient requirements can be met.

Equation 19. R E S R _ R I P P L E < V R I P P L E I R I P P L E = 26 m V 5.95 A = 4.4 m Ω
Equation 20. R E S R _ T R A N S < V T R A N S I S T E P = 99 m V 10 A = 9.9 m Ω