JAJSNB7 march   2023 TPS548C26

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 絶対最大定格
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO and Using an External Bias on VCC and VDRV Pin
      2. 7.3.2  Input Undervoltage Lockout (UVLO)
        1. 7.3.2.1 Fixed VCC_OK UVLO
        2. 7.3.2.2 Fixed VDRV UVLO
        3. 7.3.2.3 Fixed PVIN UVLO
        4. 7.3.2.4 Enable
      3. 7.3.3  Set the Output Voltage
      4. 7.3.4  Differential Remote Sense and Feedback Divider
      5. 7.3.5  Start-up and Shutdown
      6. 7.3.6  Loop Compensation
      7. 7.3.7  Set Switching Frequency and Operation Mode
      8. 7.3.8  Switching Node (SW)
      9. 7.3.9  Overcurrent Limit and Low-side Current Sense
      10. 7.3.10 Negative Overcurrent Limit
      11. 7.3.11 Zero-Crossing Detection
      12. 7.3.12 Input Overvoltage Protection
      13. 7.3.13 Output Undervoltage and Overvoltage Protection
      14. 7.3.14 Overtemperature Protection
      15. 7.3.15 Power Good
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Auto-Skip Eco-mode Light Load Operation
      3. 7.4.3 Powering the Device from a 12-V Bus
      4. 7.4.4 Powering the Device From a Split-rail Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection
        2. 8.2.3.2 Input Capacitor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 VCC and VRDV Bypass Capacitor
        5. 8.2.3.5 BOOT Capacitor Selection
        6. 8.2.3.6 PG Pullup Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS548C26 Evaluation Board
  9. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.1 Internal VCC LDO and Using an External Bias on VCC and VDRV Pin

The TPS548C26 device has an internal 4.5-V LDO featuring input from the AVIN pin and output to the VCC pin. When the AVIN voltage rises, the internal LDO is enabled automatically and starts regulating the LDO output voltage on the VCC pin. The VCC voltage provides the bias voltage for the internal analog circuitry on the controller side, and the VDRV voltage provides the supply voltage for the power stage side.

Either the VCC or VDRV pin must be bypassed with a 2.2 μF, at least 6.3-V rating ceramic capacitor. Connecting the VCC pin decoupling capacitor to AGND is required to provide a clean ground for the analog circuitry on the controller side. Referring the VDRV pin decoupling capacitor to PGND is required to minimize the parasitic loop inductance for the driver circuitry in the power stage. Placing a 1-Ω resistor between the VCC pin and VDRV pin forms a RC filter on VCC pin, which greatly reduces the noise impact from power stage driver circuit.

An external bias ranging from 4.75 V to 5.30 V can be connected to the VDRV and VCC pin and power the IC. This enhances the efficiency of the converter because the VCC and VDRV power supply current now runs off this external bias instead of the internal linear regulator.

A VDRV UVLO circuit monitors the VDRV pin voltage and disables the switching when the VDRV voltage level falls below the VDRV UVLO falling threshold. Maintaining a stable and clean VDRV voltage is required for a smooth operation of the device.

Considerations when using an external bias on the VDRV and VCC pin are shown below:

  • Connect the external bias to VDRV pin directly. Place a 1-Ω resistor between the VCC pin and VDRV pin, then VCC is powered through the 1-Ω filtering resistor.
  • For a configuration that the VCC pin and AVIN pin are shorted together, the internal LDO is always forced off. A valid external bias is required to be connected to VDRV pin (VCC pin and AVIN pin are also powered by the same external bias through the 1-Ω filtering resistor) so that the internal analog circuits have a stable power supply rail at their power enable.
  • For a configuration that the AVIN pin is not shorted to VCC pin, when the external bias is applied on the VDRV pin earlier than AVIN rail (VCC pin is also powered by the same external bias through the 1-Ω filtering resistor), the internal LDO is always forced off and the internal analog circuits have a stable power supply rail at their power enable.
  • The VCC and VDRV pins must be powered by the same source, either the internal VCC LDO, or the same external bias.
  • (Not recommended) When the external bias is applied on the VDRV pin late (for example, after AVIN rail ramp-up), any power-up and power-down sequencing can be applied as long as there is no excess current pulled out of the VCC pin. Understand that an external discharge path on the VCC or VDRV pin, which can pull a current higher than the current limit of the internal LDO, can potentially turn off VCC LDO thereby shutting off the converter output.
  • A good configuration is: Place a 1-Ω resistor between the VCC pin and VDRV pin, and shorting the AVIN pin to VCC pin.
  • A good power-up sequence with above configuration is: The external 5-V bias is applied to VDRV pin first (VCC pin is also powered by the same external bias through the 1-Ω filtering resistor), then the 12-V bus applied on PVIN pin, and then the EN signal goes high.