JAJSNB7 march   2023 TPS548C26

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 絶対最大定格
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO and Using an External Bias on VCC and VDRV Pin
      2. 7.3.2  Input Undervoltage Lockout (UVLO)
        1. 7.3.2.1 Fixed VCC_OK UVLO
        2. 7.3.2.2 Fixed VDRV UVLO
        3. 7.3.2.3 Fixed PVIN UVLO
        4. 7.3.2.4 Enable
      3. 7.3.3  Set the Output Voltage
      4. 7.3.4  Differential Remote Sense and Feedback Divider
      5. 7.3.5  Start-up and Shutdown
      6. 7.3.6  Loop Compensation
      7. 7.3.7  Set Switching Frequency and Operation Mode
      8. 7.3.8  Switching Node (SW)
      9. 7.3.9  Overcurrent Limit and Low-side Current Sense
      10. 7.3.10 Negative Overcurrent Limit
      11. 7.3.11 Zero-Crossing Detection
      12. 7.3.12 Input Overvoltage Protection
      13. 7.3.13 Output Undervoltage and Overvoltage Protection
      14. 7.3.14 Overtemperature Protection
      15. 7.3.15 Power Good
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Auto-Skip Eco-mode Light Load Operation
      3. 7.4.3 Powering the Device from a 12-V Bus
      4. 7.4.4 Powering the Device From a Split-rail Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection
        2. 8.2.3.2 Input Capacitor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 VCC and VRDV Bypass Capacitor
        5. 8.2.3.5 BOOT Capacitor Selection
        6. 8.2.3.6 PG Pullup Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS548C26 Evaluation Board
  9. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.13 Output Undervoltage and Overvoltage Protection

The TPS548C26 device monitors the FB node voltage (VFB − VGOSNS) to provide overvoltage (OV) and undervoltage (UV) protection.

VOUT UVF

When the FB node voltage (VFB − VGOSNS) drops to 600 mV or lower, the UVF comparator detects and an internal UVF Response Delay counter begins. When the 16 µs UVF Response Delay expires, the device responds per the fault response selected through SS pin. With the Latch-off response selected, the device latches OFF both high-side and low-side FETs. The latch is cleared with a reset of VCC or by toggling the EN pin. With the Hiccup response selected, the device enters hiccup mode and re-starts automatically after a hiccup sleep time of 56 ms, without limitation on the number of restart attempts.

The UVF function is enabled only after the soft-start period completes.

During the UVF Response Delay, if the FB node voltage (VFB − VGOSNS) rises above the UVF threshold, thus not qualified for a UVF event, the UVF response delay timer resets to zero. When the VOUT drops below the UVF threshold again, the UVF response delay timer re-starts from zero.

VOUT OVF

When the FB node voltage (VFB − VGOSNS) rises to 950 mV or higher, the OVF comparator detects and the device immediately latches OFF the high-side FET and turns on the low-side FET until the current flowing through low-side FET exceeds the negative overcurrent (NOC) limit. Upon reaching the −16-A NOC limit, the low-side FET is turned off, and the high-side FET is turned on again for an on-time determined by PVIN, VOUT, and fSW setting. The device operates in this cycle until the output voltage is fully discharged. After VOUT is fully discharged, the high-side FET is latched OFF and the low-side FET is latched ON. With the Latch-off response selected, the device is kept under the state of the high-side FET latched OFF and the low-side FET latched ON. The latch is cleared with a reset of VCC or by toggling the EN pin. With the Hiccup response selected, the device still discharges output voltage by running the NOC operation. However, the device re-starts automatically after a hiccup sleep time of 56 ms, without limitation on the number of restart attempts. The hiccup sleep time counter starts right after the OVF trigger.

The OVF function is enabled only after the soft-start period completes.