SLVS847A November   2008  – December 2016 TPS54917

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Lockout (UVLO)
      2. 8.3.2  Slow Start or Enable (SS/ENA)
      3. 8.3.3  VBIAS Regulator (VBIAS)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Oscillator and PWM Ramp
      6. 8.3.6  Error Amplifier
      7. 8.3.7  PWM Control
      8. 8.3.8  Dead-Time Control and MOSFET Drivers
      9. 8.3.9  Overcurrent Protection
      10. 8.3.10 Thermal Shutdown
      11. 8.3.11 Power Good (PWRGD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 PWM Operation
      2. 8.4.2 Standby Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Component Selection
        2. 9.2.2.2 Input Filter
        3. 9.2.2.3 Feedback Circuit
        4. 9.2.2.4 Operating Frequency
        5. 9.2.2.5 Output Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Estimated Circuit Area
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Developmental Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RUV Package
34-Pin VQFN
Top View
TPS54917 po_lvs847.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND 1 — Analog ground. Return for compensation network or output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin. Connect PowerPAD to AGND.
BOOT 5 O Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver.
COMP 3 I/O Error amplifier output. Connect frequency compensation network from COMP to VSENSE.
PH 6, 7, 8, 9, 10, 11, 12 O Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PGND 13, 14, 15, 16, 17, 18, 19, 20, 30, 31, 32, 33, 34 — Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection to AGND is recommended.
PWRGD 4 O Power good open-drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or internal shutdown signal active.
RT 29 I Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
SS/ENA 27 I/O Slow-start/enable input or output. Dual function pin which provides logic input to enable or disable device operation and capacitor input to externally set the start-up time.
SYNC 28 I Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin.
VBIAS 26 O Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low ESR, 0.1-µF to 1-µF ceramic capacitor.
VIN 21, 22, 23, 24, 25 I Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high-quality, low-ESR 10-µF ceramic capacitor.
VSENSE 2 I Error amplifier inverting input. Connect to output voltage compensation network or output divider.