SLVSEQ0A May   2019  – March 2020 TPS54A24

PRODUCTION DATA.  

  1. Features
  2. Applications
    1.     Simplified Schematic
  3. Description
    1.     Efficiency (VIN = 12 V, fSW = 500 kHz)
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Continuous Conduction Mode Operation (CCM)
      3. 7.3.3  VIN Pins and VIN UVLO
      4. 7.3.4  Voltage Reference and Adjusting the Output Voltage
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjustable UVLO
      7. 7.3.7  Soft Start and Tracking
      8. 7.3.8  Safe Start-Up Into Prebiased Outputs
      9. 7.3.9  Power Good
      10. 7.3.10 Sequencing (SS/TRK)
      11. 7.3.11 Adjustable Switching Frequency (RT Mode)
      12. 7.3.12 Synchronization (CLK Mode)
      13. 7.3.13 Bootstrap Voltage and 100% Duty Cycle Operation (BOOT)
      14. 7.3.14 Output Overvoltage Protection (OVP)
      15. 7.3.15 Overcurrent Protection
        1. 7.3.15.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.15.2 Low-Side MOSFET Overcurrent Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Output Voltage Resistors Selection
        7. 8.2.2.7  Soft-Start Capacitor Selection
        8. 8.2.2.8  Undervoltage Lockout Setpoint
        9. 8.2.2.9  Bootstrap Capacitor Selection
        10. 8.2.2.10 PGOOD Pullup Resistor
        11. 8.2.2.11 Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Input Capacitor

The TPS54A24 requires input decoupling ceramic capacitors type X5R, X7R or similar from VIN to PGND placed as close as possible to the IC. A total of at least 10 µF of capacitance is required and some applications may require a bulk capacitance. At least 1 µF of bypass capacitance is recommended near both VIN pins to minimize the input voltage ripple. A 0.1-µF to 1-µF capacitor must be placed by both VIN pins 2-3 and 16-17 to provide high frequency bypass to reduce the high frequency overshoot and undershoot on VIN and SW pins. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum RMS input current of the TPS54A24. The RMS input current can be calculated using Equation 23.

For this example design, a ceramic capacitor with at least a 25-V voltage rating is required to support the maximum input voltage. Two 10-µF, 1210, X7R, 25-V and two 0.1-μF, 0603, X7R 25-V capacitors in parallel has been selected to be placed on both sides of the TPS54A24 near both VIN pins to PGND pins. Based on the capacitor manufacturer's website, the total ceramic input capacitance derates to 14 µF at the nominal input voltage of 12 V. A 100-µF bulk capacitance is also used in this circuit to bypass long leads when connected a lab bench top power supply.

The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 24. The maximum input ripple occurs when operating nearest to 50% duty cycle. Using the nominal design example values of Ioutmax = 10 A, CIN = 14 μF, and fSW = 500 kHz, the input voltage ripple with the 12 V nominal input is 150 mV and the RMS input ripple current with the 4.5 V minimum input is 4.9 A.

Equation 23. TPS54A24 eq20_icir_lv46.gif

vertical spacer

Equation 24. TPS54A24 EQ_Vin_ripple_slvsdc9.gif