SLVSEQ0A May   2019  – March 2020 TPS54A24

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Simplified Schematic
  3. 3 Description
    1.     Efficiency (VIN = 12 V, fSW = 500 kHz)
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Continuous Conduction Mode Operation (CCM)
      3. 7.3.3  VIN Pins and VIN UVLO
      4. 7.3.4  Voltage Reference and Adjusting the Output Voltage
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjustable UVLO
      7. 7.3.7  Soft Start and Tracking
      8. 7.3.8  Safe Start-Up Into Prebiased Outputs
      9. 7.3.9  Power Good
      10. 7.3.10 Sequencing (SS/TRK)
      11. 7.3.11 Adjustable Switching Frequency (RT Mode)
      12. 7.3.12 Synchronization (CLK Mode)
      13. 7.3.13 Bootstrap Voltage and 100% Duty Cycle Operation (BOOT)
      14. 7.3.14 Output Overvoltage Protection (OVP)
      15. 7.3.15 Overcurrent Protection
        1. 7.3.15.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.15.2 Low-Side MOSFET Overcurrent Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Output Voltage Resistors Selection
        7. 8.2.2.7  Soft-Start Capacitor Selection
        8. 8.2.2.8  Undervoltage Lockout Setpoint
        9. 8.2.2.9  Bootstrap Capacitor Selection
        10. 8.2.2.10 PGOOD Pullup Resistor
        11. 8.2.2.11 Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.10 Sequencing (SS/TRK)

Many of the common power supply sequencing methods can be implemented using the SS/TRK, EN and PGOOD pins.

The sequential method is illustrated in Figure 28 using two TPS54A24 or similar devices. The power good of the first device is coupled to the EN pin of the second device which enables the second power supply once the primary supply reaches regulation.

Figure 29 shows the method implementing ratiometric sequencing by connecting the SS/TRK pins of two devices together. The regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start time the current source must be doubled in Equation 4.

TPS54A24 fd_seq_startup_slvseq0-tps54A24.gifFigure 28. Sequential Start-Up Sequence
TPS54A24 fd_ratio_startup_slvseq0-tps54A24.gifFigure 29. Ratiometric Start-Up Sequence

Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network of RTRT and RTRB shown in Figure 30 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the VOUT2 slightly before, after or at the same time as VOUT1. Equation 5 is the voltage difference between VOUT1 and VOUT2.

To design a ratiometric start-up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2 reaches regulation, use a negative number in Equation 6 and Equation 7 for ΔV. Equation 5 results in a positive number for applications where the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved.

The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TRK to FB offset (Vssoffset = 25 mV) in the soft-start circuit and the offset created by the pullup current source (Iss = 5 μA) and tracking resistors, the Vssoffset and Iss are included as variables in the equations.

When the TPS54A24 is enabled, an internal switch at the SS/TRK pin turns on to discharge the SS/TRK voltage to near ground as described in Soft Start and Tracking. The SS/TRK pin voltage must discharge low enough before the TPS54A24 starts up. If there is voltage on VOUT1 and the upper resistor at the SS/TRK pin is too small, the SS/TRK pin cannot discharge low enough and VOUT2 does not ramp up. The upper resistor in the SS/TRK divider may need to be increased to allow the SS/TRK pin to drop close enough to ground. To ensure proper startup of VOUT2 , the calculated RTRT value from Equation 6 must be greater than the value calculated in Equation 8. Calculate RTRB using the final value of RTRT.

Equation 5. TPS54A24 EQ_ratio_simul_deltaV_slvsdc9.gif

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Equation 6. TPS54A24 EQ_Rtr_top_slvsdc9.gif

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Equation 7. TPS54A24 EQ_Rtr_bot_slvsdc9.gif

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Equation 8. TPS54A24 eq_rtr-top_max_slvseq0-tps54A24.gif

As described in Power Good, for the PGOOD output to be active the SS/TRK voltage must be above 0.75 V. The external divider may prevent the SS/TRK voltage from charging above the threshold. For the SS/TRK pin to charge above the threshold, a switch may be needed to disconnect the resistor divider or modify the resistor divider ratio of the VOUT2 converter after start-up is complete. The PGOOD pin of the VOUT1 converter could be used for this. One solution is to add a resistor from SS/TRK of the VOUT2 converter to the PGOOD of the VOUT1 converter. While the PGOOD of VOUT1 pulls low, this resistor is in parallel with RTRB. When VOUT1 is in regulation its PGOOD pin will float. If the PGOOD pin of VOUT1 is connected to a pullup voltage, make sure to include this in calculations. A second option is to use the PGOOD pin to turn on or turn off the external switch to change the divide ratio.

TPS54A24 fd_ratio_simul_startup_slvseq0-tps54A24.gifFigure 30. Ratiometric and Simultaneous Start-Up Sequence