JAJSNP4A May   2023  – February 2024 TPS54KB20

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Internal VCC LDO and Using External Bias On the VCC Pin
      2. 6.3.2  Enable
      3. 6.3.3  Adjustable Soft Start
      4. 6.3.4  Power Good
      5. 6.3.5  Output Voltage Setting
      6. 6.3.6  Remote Sense
      7. 6.3.7  D-CAP4 Control
      8. 6.3.8  Multifunction Select (MSEL) Pin
      9. 6.3.9  Low-side MOSFET Zero-Crossing
      10. 6.3.10 Current Sense and Positive Overcurrent Protection
      11. 6.3.11 Low-side MOSFET Negative Current Limit
      12. 6.3.12 Overvoltage and Undervoltage Protection
      13. 6.3.13 Output Voltage Discharge
      14. 6.3.14 UVLO Protection
      15. 6.3.15 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Auto-Skip Eco-mode Light Load Operation
      2. 6.4.2 Forced Continuous-Conduction Mode
      3. 6.4.3 Powering the Device From a Single Bus
      4. 6.4.4 Powering the Device From a Split-rail Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Output Voltage Setting Point
        2. 7.2.2.2  Choose the Switching Frequency and the Operation Mode
        3. 7.2.2.3  Choose the Inductor
        4. 7.2.2.4  Set the Current Limit (ILIM)
        5. 7.2.2.5  Choose the Output Capacitor
        6. 7.2.2.6  RAMP Selection
        7. 7.2.2.7  Choose the Input Capacitors (CIN)
        8. 7.2.2.8  Soft-Start Capacitor (SS Pin)
        9. 7.2.2.9  EN Pin Resistor Divider
        10. 7.2.2.10 VCC Bypass Capacitor
        11. 7.2.2.11 BOOT Capacitor
        12. 7.2.2.12 RC Snubber
        13. 7.2.2.13 PG Pullup Resistor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.2.7 Choose the Input Capacitors (CIN)

The device requires input bypass capacitors between both pairs of VIN and PGND pins to bypass the power-stage. The bypass capacitors must be placed as close as possible to the pins of the IC as the layout allows. At least 20µF nominal of ceramic capacitance and two high frequency ceramic bypass capacitors are required. This device has a hard limit of 20µF. Some applications can require greater capacitance and can even require a bulk capacitor. Derating can impact the effective input capacitance value. A 0.1μF to 1μF capacitor must be placed as close as possible to both VIN pins 3 and 9 on the same side of the board of the device to provide the required high frequency bypass, to reduce the high frequency overshoot and undershoot across the power-stage from VIN to SW and SW to PGND. TI recommends at least 1μF of bypass capacitance as close as possible to each VIN pin to minimize the input voltage ripple. The ceramic capacitors must be a high-quality dielectric of X6S or better for the high capacitance-to-volume ratio and stable characteristics across temperature. In addition to this requirement, more bulk capacitance can be needed on the input depending on the application to minimize variations on the input voltage during transient conditions.

The input capacitance required to meet a specific input ripple target can be calculated with Equation 32. A recommended target input voltage ripple is 5% the minimum input voltage, 225mV in this example. The calculated input capacitance is 27.2μF and this meets the minimum input capacitance of 20µF.

Equation 32. C I N > V O U T × I O U T × 1 - V O U T V I N m i n f S W × V I N m i n × V I N _ R I P P L E = 3.3   V × 25   A × 1 - 3.3   V 4.5   V 800   k H z × 4.5   V × 225   m V = 27.2   μ F

The capacitor must also have an RMS current rating greater than the maximum input RMS current in the application. The input RMS current the input capacitors must support is calculated by Equation 34 and is 11.2A in this example. The ceramic input capacitors have a current rating greater than this value.

Equation 33. I C I N ( R M S ) = V O U T V I N m i n × V I N m i n - V O U T V I N m i n × I O U T 2 + I R I P P L E 2 12 =
Equation 34. I C I N ( R M S ) = 3.3   V 4.5   V × 4.5   V - 3.3   V 4.5   V × 25 2 + 7 2 12 = 11.2   A

For applications requiring bulk capacitance on the input, such as ones with low input voltage and high current, TI recommends the selection process in How to select input capacitors for a buck converter analog design journal.