JAJSNP4A May   2023  – February 2024 TPS54KB20

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Internal VCC LDO and Using External Bias On the VCC Pin
      2. 6.3.2  Enable
      3. 6.3.3  Adjustable Soft Start
      4. 6.3.4  Power Good
      5. 6.3.5  Output Voltage Setting
      6. 6.3.6  Remote Sense
      7. 6.3.7  D-CAP4 Control
      8. 6.3.8  Multifunction Select (MSEL) Pin
      9. 6.3.9  Low-side MOSFET Zero-Crossing
      10. 6.3.10 Current Sense and Positive Overcurrent Protection
      11. 6.3.11 Low-side MOSFET Negative Current Limit
      12. 6.3.12 Overvoltage and Undervoltage Protection
      13. 6.3.13 Output Voltage Discharge
      14. 6.3.14 UVLO Protection
      15. 6.3.15 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Auto-Skip Eco-mode Light Load Operation
      2. 6.4.2 Forced Continuous-Conduction Mode
      3. 6.4.3 Powering the Device From a Single Bus
      4. 6.4.4 Powering the Device From a Split-rail Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Output Voltage Setting Point
        2. 7.2.2.2  Choose the Switching Frequency and the Operation Mode
        3. 7.2.2.3  Choose the Inductor
        4. 7.2.2.4  Set the Current Limit (ILIM)
        5. 7.2.2.5  Choose the Output Capacitor
        6. 7.2.2.6  RAMP Selection
        7. 7.2.2.7  Choose the Input Capacitors (CIN)
        8. 7.2.2.8  Soft-Start Capacitor (SS Pin)
        9. 7.2.2.9  EN Pin Resistor Divider
        10. 7.2.2.10 VCC Bypass Capacitor
        11. 7.2.2.11 BOOT Capacitor
        12. 7.2.2.12 RC Snubber
        13. 7.2.2.13 PG Pullup Resistor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.4.4 Powering the Device From a Split-rail Configuration

When an external bias, which is at a different level from main VIN bus, is applied onto the VCC pin the device can be configured to split-rail by using both the main VIN bus and the VCC bias. Connecting a valid VCC bias to the VCC pin overrides the internal LDO, thus saves power loss on the internal LDO. This configuration helps to improve overall system level efficiency but requires a valid VCC bias. A 3.3V or 5.0V rail is the common choice as VCC bias. With a stable VCC bias, the recommended VIN input range under this configuration remains the same, from 4.0V to 16V.

The noise of the external bias affects the internal analog circuitry. To make sure of a proper operation, a clean, low-noise external bias and good local decoupling capacitor from VCC pin to PGND pin are required. Figure 6-10 shows an example for this split rail configuration.

The VCC external bias current during nominal operation varies with the bias voltage level and also the operating frequency. For example, by setting the device to skip-mode, the VCC pin draws less current from the external bias when the frequency decreases under a light load condition. The typical VCC external bias current under FCCM operation is listed in Electrical Characteristics. The external bias must be capable of supplying this current or the external bias voltage can drop and the internal LDO can no longer be overridden by it.

Under split rail configuration, VIN, VCC bias, and EN are the signals to enable the part. For start-up sequence, TI recommends that at least one of VIN UVLO rising threshold or EN rising threshold is satisfied later than VCC UVLO rising threshold. A practical start-up sequence example is:

  1. VIN applied
  2. External VCC bias applied
  3. EN signal goes high

Similarly, for power-down sequence, TI recommends that at least one of the VIN UVLO falling threshold or the EN falling threshold is satisfied before the external VCC bias supply turns off. If the external VCC bias supply turns off first, the internal LDO of the device prevents the VCC voltage from dropping below 3.0-V and be loaded by other circuits powered by the external VCC bias supply.

GUID-20230427-SS0I-FCZJ-705S-TH8HL2MWTS8F-low.svg Figure 6-10 Split-Rail Configuration With External VCC Bias