JAJSQV6 February 2024 TPS54KC23
PRODUCTION DATA
The TPS54KC23 has an internal 3.0V LDO featuring input from VIN and output to VCC. When the EN voltage rises above the enable threshold (VEN(R)), the internal LDO is enabled and starts regulating output voltage on the VCC pin. The VCC voltage provides the bias voltage for the internal analog circuitry and also provides the supply voltage for the gate drivers.
Bypass the VCC pin with a 1µF, at least 6.3V rating ceramic capacitor. An external bias that is above the output voltage of the internal LDO can override the internal LDO. This action enhances the efficiency of the converter because the VCC current now runs off this external bias instead of the internal linear regulator. An external bias of 5.0V can be used to provide additional efficiency enhancement by reducing the RDSON of the integrated power MOSFETs.
The VCC UVLO circuit monitors the VCC pin voltage and disables the whole converter when VCC falls below the VCC UVLO falling threshold. Maintaining a stable and clean VCC voltage is required for a smooth operation of the device.
Considerations when using an external bias on the VCC pin are as follows: