JAJSQV6 February 2024 TPS54KC23
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY | ||||||
IQ(VIN) | VIN quiescent current | Non-switching, VEN = 2V, VFB = VFB_REG + 10mV, no external bias on VCC pin | 940 | 1200 | µA | |
IQ(VIN) | VIN quiescent current with external VCC bias | VIN = 12V, VEN = 2V, VFB = VFB_REG + 10mV (non-switching), 3.3V external bias on VCC pin | 230 | 350 | µA | |
IQ(VCC) | VCC quiescent current | VIN = 12V, VEN = 2V, VFB = VFB_REG + 10mV (non-switching), 3.3V external bias on VCC pin | 820 | 1000 | µA | |
ISD(VIN) | VIN shutdown supply current | VIN = 12V, VEN = 0V, no external bias on VCC pin | 9 | 20 | µA | |
ISD(VCC) | VCC shutdown current | VEN = 0V, VIN = 0V, 3.3V external bias on VCC pin | 90 | 140 | µA | |
IVCC | VCC external bias current | TJ = 25°C, VIN = 12V, VEN = 2V, regular switching, RMSEL = 10.5kΩ, fSW = 800kHz, 3.3V external bias on VCC pin | 12 | mA | ||
TJ = 25°C, VIN = 12V, VEN = 2V, regular switching, RMSEL = 13.3kΩ, fSW = 1100kHz, 3.3V external bias on VCC pin | 16 | mA | ||||
TJ = 25°C, VIN = 12V, VEN = 2V, regular switching, RMSEL = 30.1kΩ, fSW = 1400kHz, 3.3V external bias on VCC pin | 20.5 | mA | ||||
UVLO | ||||||
VINUVLO(R) | VIN UVLO rising threshold | VIN rising | 3.87 | 3.95 | V | |
VINUVLO(F) | VIN UVLO falling threshold | VIN falling | 3.60 | 3.70 | V | |
VINUVLO(H) | VIN UVLO hysteresis | 0.17 | V | |||
ENABLE | ||||||
VEN(R) | EN voltage rising threshold | EN rising, enable switching | 1.18 | 1.23 | V | |
VEN(F) | EN voltage falling threshold | EN falling, disable switching | 0.95 | 1 | V | |
VEN(H) | EN voltage hysteresis | 0.18 | V | |||
EN internal pull-down resistance | EN pin to AGND | 0.74 | 1 | 1.27 | MΩ | |
VENSTB(R) | EN standby rising threshold | EN rising, enable internal LDO, no switching | 0.75 | 1.0 | V | |
VENSTB(F) | EN standby falling threshold | EN falling, disable internal LDO | 0.5 | 0.6 | V | |
INTERNAL LDO (VCC) | ||||||
VVCC | Internal LDO output voltage | Non-switching, IVCC = 25mA | 2.82 | 2.94 | 3.05 | V |
IVCC | Internal LDO short-circuit current limit | VVIN = 10V | 100 | 275 | mA | |
VCCUVLO(R) | VCC UVLO rising threshold | VVIN = 4V | 2.7 | 2.82 | V | |
VCCUVLO(F) | VCC UVLO falling threshold | VVIN = 4V | 2.45 | 2.55 | V | |
VCCUVLO(H) | VCC UVLO hysteresis | VVIN = 4V | 0.15 | V | ||
FB threshold to turn off VCC LDO | EN high to low | 25 | 50 | 85 | mV | |
REFERENCE VOLTAGE (FB) | ||||||
VFB_REG | Feedback regulation voltage | 497.5 | 500 | 502.5 | mV | |
IFB(LKG) | FB input leakage current | VFB = VFB_REG | 160 | nA | ||
DIFFERENTIAL REMOTE SENSE AMPLIFIER | ||||||
IGOSNS | Leakage current out of GOSNS pin | VGOSNS - VAGND = 100mV | 80 | µA | ||
VICM | GOSNS common mode voltage for regulation | VGOSNS versus VAGND | –0.1 | 0.1 | V | |
SWITCHING FREQUENCY | ||||||
fSW(FCCM) | Switching frequency, FCCM operation | VVIN = 12V, VOUT = 3.3V, RMSEL = 10.5kΩ (FCCM), No load | 680 | 800 | 920 | kHz |
VVIN = 12V, VOUT = 3.3V, RMSEL = 24.9kΩ (FCCM), No load | 910 | 1070 | 1230 | kHz | ||
VVIN = 12V, VOUT = 3.3V, RMSEL = 48.7kΩ (FCCM), No load | 1150 | 1350 | 1550 | kHz | ||
STARTUP | ||||||
ISS | Soft-start charge current | VSS = 0V | 26 | 36 | 45 | µA |
VSS(DONE) | Soft-start voltage threshold for soft-start done | TPS54KC23 | 1 | V | ||
EN HIGH to start of switching delay | CSS = 33nF, Internal VCC, CVCC = 2.2µF, RMSEL = 158kΩ, Measured from EN high to VSS = 50mV | 740 | µs | |||
POWER STAGE | ||||||
RDSON(HS) | High-side MOSFET on-resistance | VBOOT-SW = 3.0V | 5.8 | mΩ | ||
RDSON(LS) | Low-side MOSFET on-resistance | VVCC = 3.3V | 2.3 | mΩ | ||
tON(min) | Minimum ON pulse width | 40 | ns | |||
tOFF(min) | Minimum OFF pulse width (1) | 130 | 160 | ns | ||
BOOT CIRCUIT | ||||||
IBOOT(LKG) | Leakage current into BOOT pin | VVIN = 12V, VBOOT-SW = 3V, Enabled, Not switching | 23 | 31 | µA | |
OVERCURRENT PROTECTION | ||||||
OC limit high clamp | Valley current on LS FET, 0Ω ≤ RILIM ≤ 4.32kΩ | 27.8 | 30.6 | A | ||
KOCL | Constant for RILIM equation | 134000 | A×Ω | |||
ILS(OC) | Low-side valley current limit, open loop | Valley current on LS FET, RILIM = 4.32kΩ | 27.8 | 30.6 | 33.3 | A |
Valley current on LS FET, RILIM = 5.36 kΩ | 20.1 | 24.6 | 29.5 | A | ||
Valley current on LS FET, RILIM = 7.32kΩ | 14.6 | 18.0 | 21.7 | A | ||
Valley current on LS FET, RILIM = 10.7kΩ | 9.6 | 12.3 | 15.2 | A | ||
Valley current on LS FET, RILIM = 20kΩ | 4.6 | 6.6 | 8.8 | A | ||
ILS(NOC) | Low-side negative current limit, open loop | Sinking current limit on LS FET | –10 | –7.5 | A | |
RILIM | ILIM pin resistance range | 0 | 20 | kΩ | ||
IZC | Zero-cross detection current threshold to enter DCM, open loop | VIN = 12V | –700 | mA | ||
IZC(HYS) | Zero-cross detection current threshold hysteresis after entering DCM, open loop | VIN = 12V | 1000 | mA | ||
OUTPUT OVP AND UVP | ||||||
VOVP | Overvoltage-protection (OVP) threshold voltage | VFB rising | 113% | 116% | 119% | |
VUVP | Undervoltage-protection (UVP) threshold voltage | VFB falling | 76% | 79% | 82% | |
tOVPDLY | OVP delay | With 100mV overdrive | 400 | ns | ||
tUVPDLY | UVP filter delay | 70 | µs | |||
Hiccup wait time | 7 x tSS | ms | ||||
POWER GOOD | ||||||
VPGTH(RISE_OV) | Power-good threshold | FB rising, PG high to low | 113% | 116% | 119% | |
VPGTH(RISE_UV) | Power-good threshold | FB rising, PG low to high | 91% | |||
VPGTH(FALL_UV) | Power-good threshold | FB falling, PG high to low | 79% | |||
PG delay going from low to high during startup | 1.3 | ms | ||||
PG delay going from high to low | 4 | 6.2 | µs | |||
IPG(LKG) | PG pin leakage current when open drain output is high | VPG = 6V | 7 | µA | ||
PG pin output low-level voltage | IPG = 7mA | 500 | mV | |||
PG pin output low-level when VIN and VCC are low | VVIN = 0V, VVCC = 0V, VEN = 0V, IPG = 25µA | 650 | mV | |||
PG pin output low-level when VIN and VCC are low | VVIN = 0V, VVCC = 0V, VEN = 0V, IPG = 250µA | 800 | mV | |||
THERMAL SHUTDOWN | ||||||
TJ(SD) | Thermal shutdown threshold (1) | Temperature rising | 150 | 170 | °C | |
TJ(HYS) | Thermal shutdown hysteresis (1) | 13 | °C | |||
OUTPUT DISCHARGE | ||||||
Output discharge resistor on SW pin | VIN = 12V, VSW = 1V, power conversion disabled | 100 | Ω |