TPS55289 は、バッテリ電圧やアダプタ電圧を複数の電源レール向けに変換するように最適化された同期整流昇降圧コンバータです。TPS55289 は、4 個の MOSFET スイッチを内蔵しており、USB Power Delivery (USB PD) アプリケーション向けのコンパクトなソリューションを実現します。
TPS55289 は、最大 30V の入力電圧に対応できます。I2C インターフェイスにより、TPS55289 の出力電圧は、0.8V～22V の範囲で 10mV 刻みにプログラム可能です。昇圧モードでの動作時には、12V 入力電圧から 60W を供給できます。このデバイスは、9V の入力電圧から 45W を供給できます。
TPS55289 は、平均電流モード制御方式を採用しています。スイッチング周波数は、外付け抵抗で 200kHz～2.2MHz に設定することも、外部クロックに同期させることもできます。TPS55289 は、ピーク EMI を最小限にするための拡散スペクトラム・オプション機能も備えています。
TPS55289 は、出力過電圧保護、平均インダクタ電流制限、サイクルごとのピーク電流制限、出力短絡保護機能を備えています。また、TPS55289 は、持続的な過負荷状態での出力電流制限およびヒカップ・モード保護オプション機能により、安全な動作を確保しています。
TPS55289 は、高いスイッチング周波数で動作できるため、小型のインダクタとコンデンサが使えます。本デバイスは 3.0mm × 5.0mm の QFN パッケージで供給されます。
| 部品番号 | パッケージ (1) | 本体サイズ |
|---|---|---|
| TPS55289 | VQFN-HR | 3.0mm × 5.0mm |
| Pin | I/O | Description | |
|---|---|---|---|
| Name | NO. | ||
| EN/UVLO | 1 | I | Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high level enables the device. Logic low level disables the device and turns it into shutdown mode. After the voltage at the EN/UVLO pin is above the logic high voltage of 1.15 V, this pin acts as programmable UVLO input with 1.23-V internal reference. |
| MODE | 2 | I | I2C target address selection. When it is connected to the logic high voltage, the I2C target address is 74H. When it is connected to the logic low voltage, the I2C target address is 75H. |
| SCL | 3 | I | Clock of I2C interface |
| SDA | 4 | I/O | Data of I2C interface |
| DITH/SYNC | 5 | I | Dithering frequency setting and synchronous clock input. Use a capacitor between this pin and ground to set the dithering frequency. When this pin is short to ground or pulled above 1.2 V, there is no dithering function. An external clock can be applied at this pin to synchronize the switching frequency. |
| FSW | 6 | I | The switching frequency is programmed by a resistor between this pin and the AGND pin. |
| VIN | 7 | PWR | Input of the buck-boost converter |
| SW1 | 8 | PWR | The switching node pin of the buck side. It is connected to the drain of the internal buck low-side power MOSFET and the source of internal buck high-side power MOSFET. |
| PGND | 9 | PWR | Power ground of the IC |
| SW2 | 10 | PWR | The switching node pin of the boost side. It is connected to the drain of the internal boost low-side power MOSFET and the source of internal boost high-side power MOSFET. |
| VOUT | 11 | PWR | Output of the buck-boost converter |
| ISP | 12 | I | Positive input of the current sense amplifier. An optional current sense resistor connected between the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current limit setting value in the register, a slow constant current control loop becomes active and starts to regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin together with the VOUT pin can disable the output current limit function. |
| ISN | 13 | I | Negative input of the current sense amplifier. An optional current sense resistor connected between the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current limit setting value in the register, a slow constant current control loop becomes active and starts to regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin together with the VOUT pin can disable the output current limit function. |
| FB/INT | 14 | I/O | When the device is set to use external output voltage feedback, connect to the center tap of a resistor divider to program the output voltage. When the device is set to use internal feedback, this pin is a fault indicator output. When there is an internal fault happening, this pin outputs logic low level. |
| COMP | 15 | O | Output of the internal error amplifier. Connect the loop compensation network between this pin and the AGND pin. |
| CDC | 16 | O | Voltage output proportional to the sensed voltage between the ISP pin and the ISN pin. Use a resistor between this pin and AGND to increase the output voltage to compensate voltage droop across the cable caused by the cable resistance. |
| AGND | 17 | — | Signal ground of the IC |
| VCC | 18 | O | Output of the internal regulator. A ceramic capacitor of more than 4.7 μF is required between this pin and the AGND pin. |
| BOOT2 | 19 | O | Power supply for high-side MOSFET gate driver in boost side. A 0.1-µF ceramic capacitor must be connected between this pin and the SW2 pin. |
| BOOT1 | 20 | O | Power supply for high-side MOSFET gate driver in buck side. A 0.1-µF ceramic capacitor must be connected between this pin and the SW1 pin. |
| EXTVCC | 21 | I | Select the internal LDO or external 5 V for VCC. When it is connected to logic high voltage, select the internal LDO. When it is connected to logic low voltage, select the external 5 V for VCC. |