JAJSBR4E May 2012 – September 2021 TPS55340
PRODUCTION DATA
This design was compensated by measuring the frequency response of the power stage at the lowest input voltage of 6 V and choosing the components for the desired bandwidth. The lowest right half plane zero (ƒRHPZ) is calculated to be 36.7 kHz with Equation 52. Using the recommendation to limit the bandwidth to 1/3 of ƒRHPZ, the maximum recommended is 12.2 kHz.
This design also uses only one pole and one zero. To achieve approximately 60 degrees of phase margin, the power stage phase must be no lower than approximately –120 degrees at the desired bandwidth. To ensure a stable design, R3 was initially set to 1 kΩ and C4 was 1 µF. Figure 8-11 shows the measurement of the power stage. At 7 kHz the power stage has a gain of 19.52 dB and phase of –118.1 degrees.
As there are no changes in the transconductance amplifier, the equations used to calculate the external compensation components in a boost design can be used in the SEPIC design. Using the maximum Gea from the electrical specification of 440 µmho, Equation 38 calculates the nearest standard value of R3 to be 2.37 kΩ. Using Equation 39, C4 is calculated to the nearest standard value of 0.1 µF.