JAJSL54 October   2021 TPS562212

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Advanced Emulated Current Mode Control
      2. 7.3.2 Mode Selection and PG/SS Pin Function Configuration
      3. 7.3.3 Power Good (PG)
      4. 7.3.4 Soft Start and Pre-Biased Soft Start
      5. 7.3.5 Output Discharge Through PG/SS Pin
      6. 7.3.6 Precise Enable and Adjusting Undervoltage Lockout
      7. 7.3.7 Overcurrent Limit and Undervoltage Protection
      8. 7.3.8 Overvoltage Protection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 FCCM Operation
      4. 7.4.4 CCM Operation
      5. 7.4.5 DCM Operation and Eco-mode Operation
      6. 7.4.6 On-Time Extension for Large Duty Cycle Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Resistors Selection
        3. 8.2.2.3 Output Inductor Selection
        4. 8.2.2.4 Output Capacitor Selection
        5. 8.2.2.5 Input Capacitor Selection
        6. 8.2.2.6 Bootstrap Capacitor Selection
        7. 8.2.2.7 Undervoltage Lockout Set Point
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Third-Party Products Disclaimer
        2. 11.1.1.2 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.4 Output Capacitor Selection

After selecting the inductor, the output capacitor needs to be optimized. The LC filter used as the output filter has double pole at:

Equation 16. GUID-D35A4009-0D10-45C1-8249-BB64FDF9AA06-low.gif

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. A high frequency zero is introduced by the internal circuit that reduces the gain roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of fP is located below the high frequency zero, but close enough. The phase boost provided by the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement, it is better to make the L1 × COUT_E value meet the range of the L1 × COUT_E value recommended in Table 8-2.

Table 8-2 Recommended Component Values
OUTPUT VOLTAGE (V)(1) R8(2)
(kΩ)		 R9
(kΩ)		 L1(3)
(µH)		 COUT(4)
(µF)		 RANGE OF L1 × COUT_E(5)
(μH × μF)		 C7(6)
(pF)
0.76 5.36 20.0 0.68 2 × 22 17–130 —
1.05 15.0 20.0 1.0 2 × 22 17–130 10–100
1.8 40.0 20.0 1.5 1 × 22 15–160 10–100
2.5 31.6 10.0 1.8 1 × 22 15–160 10–100
3.3 45.3 10.0 2.2 1 × 22 15–160 10–100
5 73.2 10.0 3.3 1 × 22 15–160 10–100
(1) Use the recommended L1 and COUT combination of the higher and closest output rail for the unlisted output rails.
(2) R8 = 10 kΩ and R9 = Float for VOUT = 0.6 V
(3) Inductance values are calculated based on VIN=18 V, but they can also be used for other input voltages. Users can calculate their preferred inductance value per Equation 12.
(4) COUT is the sum of nominal output capacitance. 22-μF, 0805, 10-V or higher specifications capacitors are recommended.
(5) COUT_E is the effective value after derating. The value of L1 × COUT_E is recommended to be within the range.
(6) R6 and C7 can be used to improve the load transient response and improve the loop-phase margin.

The capacitor value and ESR determine the amount of output voltage ripple. The device is intended for use with ceramic or other low-ESR capacitors. Use Equation 17 to determine the required RMS current rating for the output capacitor.

Equation 17. GUID-22FFDC5F-D1E4-4B85-B6F1-4E93C57D1B4A-low.gif

Two Murata GRM21BR61C226ME44L 22-μF, 0805, 16-V output capacitors are used for this design. From the data sheet, the estimated DC derating rate is 66.8% at room temperature with AC voltage of 0.2 V. The total output effective capacitance is approximately 14.7 μF. The value of L1 × COUT_E is 33 μH × μF, which is within the recommended range.