JAJSI75A April   2018  – November 2019 TPS57112C-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics Curves
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fixed-Frequency PWM Control
      2. 8.3.2 Slope Compensation and Output Current
      3. 8.3.3 Bootstrap Voltage (BOOT) and Low-Dropout Operation
        1. 8.3.3.1 Error Amplifier
      4. 8.3.4 Voltage Reference
    4. 8.4 Device Functional Modes
      1. 8.4.1  Adjusting the Output Voltage
      2. 8.4.2  Enable Functionality and Adjusting Undervoltage Lockout
      3. 8.4.3  Slow-Start or Tracking Pin
      4. 8.4.4  Sequencing
      5. 8.4.5  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      6. 8.4.6  Overcurrent Protection
      7. 8.4.7  Frequency Shift
      8. 8.4.8  Reverse Overcurrent Protection
      9. 8.4.9  Synchronize Using the RT/CLK Pin
      10. 8.4.10 Power Good (PWRGD Pin)
      11. 8.4.11 Overvoltage Transient Protection
      12. 8.4.12 Thermal Shutdown
      13. 8.4.13 Small-Signal Model for Loop Response
      14. 8.4.14 Simple Small-Signal Model for Peak-Current-Mode Control
      15. 8.4.15 Small-Signal Model for Frequency Compensation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Switching Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor
        4. 9.2.2.4 Input Capacitor
        5. 9.2.2.5 Slow-Start Capacitor
        6. 9.2.2.6 Bootstrap Capacitor Selection
        7. 9.2.2.7 Output Voltage and Feedback Resistor Selection
        8. 9.2.2.8 Compensation
        9. 9.2.2.9 Power-Dissipation Estimate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

TJ = –40°C to +150°C, VIN = 2.95 V to 6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Internal undervoltage lockout threshold VIN UVLO START (output turns on, device starts switching) 2.45 2.6 V
VIN UVLO STOP (output turns off, device stops switching) 2.28 2.5
Shutdown supply current V(EN) = 0 V, 25°C, 2.95 V ≤ V(VIN) ≤ 6 V 5.5 15 μA
Quiescent current – I(q) V(VSENSE) = 0.9 V, V(VIN) = 5 V, 25°C, Rt = 400 kΩ 515 750 μA
ENABLE AND UVLO (EN PIN)
Enable threshold Rising 1.25 V
Falling 1.18
Input current Enable threshold + 50 mV –3.2 μA
Enable threshold – 50 mV –1.65
VOLTAGE REFERENCE (VSENSE PIN)
Voltage reference 2.95 V ≤ V(VIN) ≤ 6 V, –40°C <TJ < +150°C 0.79 0.8 0.811 V
MOSFET
High-side switch resistance BOOT-PH = 5 V 12 30 mΩ
BOOT-PH = 2.95 V 16 30
Low-side switch resistance V(VIN) = 5 V 13 30 mΩ
V(VIN) = 2.95 V 17 30
ERROR AMPLIFIER
Input current 2 nA
Error amplifier transconductance (gm) –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V 245 µS
Error amplifier transconductance (gm) during slow start –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V,
V(VSENSE) = 0.4 V		 79 µS
Error amplifier source or sink V(COMP) = 1 V, 100-mV overdrive ±20 μA
COMP to high-side FET current gm 14 S
CURRENT LIMIT
Current-limit threshold 2.9 5.3 A
THERMAL SHUTDOWN
Thermal shutdown 168 °C
Hysteresis 20 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using Rt mode 200 2000 kHz
Switching frequency Rt = 400 kΩ 400 500 600 kHz
Switching frequency range using CLK mode 300 2000 kHz
RT/CLK voltage Rt = 400 kΩ 0.5 V
RT/CLK high threshold 1.6 2.5 V
Delay from RT/CLK falling edge to PH rising edge Measure at 500 kHz with Rt resistor in series with device pin 90 ns
BOOT (BOOT PIN)
BOOT charge resistance V(VIN) = 5 V 16 Ω
BOOT-PH UVLO V(VIN) = 2.95 V 2.1 V
SLOW START AND TRACKING (SS/TR PIN)
Charge current V(SS/TR) = 0.4 V 2 μA
SS/TR to VSENSE matching V(SS/TR) = 0.4 V 54 mV
SS/TR to reference crossover 98% of nominal reference voltage 1.1 V
SS/TR discharge voltage (overload) V(VSENSE) = 0 V 60 mV
SS/TR discharge current (overload) V(VSENSE) = 0 V, V(SS/TR) = 0.4 V 350 µA
SS discharge current (UVLO, EN, thermal fault) V(VIN) = 5 V, V(SS/TR) = 0.5 V 1.9 mA
POWER GOOD (PWRGD PIN)
VSENSE threshold V(VSENSE) falling (Fault) 91 %Vref
V(VSENSE) rising (Good) 93
V(VSENSE) rising (Fault) 109
V(VSENSE) falling (Good) 107
Hysteresis V(VSENSE) falling 2 %Vref
Output-high leakage V(VSENSE) = Vref, V(PWRGD) = 5.5 V 7 nA
On-resistance 56 100 Ω
Output low I(PWRGD) = 3 mA 0.3 V
Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 μA 0.65 1.5 V