JAJSI75A April   2018  – November 2019 TPS57112C-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics Curves
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fixed-Frequency PWM Control
      2. 8.3.2 Slope Compensation and Output Current
      3. 8.3.3 Bootstrap Voltage (BOOT) and Low-Dropout Operation
        1. 8.3.3.1 Error Amplifier
      4. 8.3.4 Voltage Reference
    4. 8.4 Device Functional Modes
      1. 8.4.1  Adjusting the Output Voltage
      2. 8.4.2  Enable Functionality and Adjusting Undervoltage Lockout
      3. 8.4.3  Slow-Start or Tracking Pin
      4. 8.4.4  Sequencing
      5. 8.4.5  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      6. 8.4.6  Overcurrent Protection
      7. 8.4.7  Frequency Shift
      8. 8.4.8  Reverse Overcurrent Protection
      9. 8.4.9  Synchronize Using the RT/CLK Pin
      10. 8.4.10 Power Good (PWRGD Pin)
      11. 8.4.11 Overvoltage Transient Protection
      12. 8.4.12 Thermal Shutdown
      13. 8.4.13 Small-Signal Model for Loop Response
      14. 8.4.14 Simple Small-Signal Model for Peak-Current-Mode Control
      15. 8.4.15 Small-Signal Model for Frequency Compensation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Switching Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor
        4. 9.2.2.4 Input Capacitor
        5. 9.2.2.5 Slow-Start Capacitor
        6. 9.2.2.6 Bootstrap Capacitor Selection
        7. 9.2.2.7 Output Voltage and Feedback Resistor Selection
        8. 9.2.2.8 Compensation
        9. 9.2.2.9 Power-Dissipation Estimate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.3 Bootstrap Voltage (BOOT) and Low-Dropout Operation

The TPS57112C-Q1 device has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. The value of the ceramic capacitor should be 0.1 μF. TI recommends a ceramic capacitor with a voltage rating of 10 V or higher, and an X7R or X5R grade dielectric because of the stable characteristics over temperature and voltage.

To improve dropout, the TPS57112C-Q1 device operates at 100% duty cycle as long as the BOOT-to-PH pin voltage is greater than 2.2 V. A UVLO circuit turns off the high-side MOSFET, allowing for the low-side MOSFET to conduct when the voltage from BOOT to PH drops below 2.2 V. Because the supply current sourced from the BOOT pin is low, the high-side MOSFET can remain on for more switching cycles than are required to refresh the capacitor; thus, the effective duty cycle of the switching regulator is high.