JAJSI75A April   2018  – November 2019 TPS57112C-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics Curves
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fixed-Frequency PWM Control
      2. 8.3.2 Slope Compensation and Output Current
      3. 8.3.3 Bootstrap Voltage (BOOT) and Low-Dropout Operation
        1. 8.3.3.1 Error Amplifier
      4. 8.3.4 Voltage Reference
    4. 8.4 Device Functional Modes
      1. 8.4.1  Adjusting the Output Voltage
      2. 8.4.2  Enable Functionality and Adjusting Undervoltage Lockout
      3. 8.4.3  Slow-Start or Tracking Pin
      4. 8.4.4  Sequencing
      5. 8.4.5  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      6. 8.4.6  Overcurrent Protection
      7. 8.4.7  Frequency Shift
      8. 8.4.8  Reverse Overcurrent Protection
      9. 8.4.9  Synchronize Using the RT/CLK Pin
      10. 8.4.10 Power Good (PWRGD Pin)
      11. 8.4.11 Overvoltage Transient Protection
      12. 8.4.12 Thermal Shutdown
      13. 8.4.13 Small-Signal Model for Loop Response
      14. 8.4.14 Simple Small-Signal Model for Peak-Current-Mode Control
      15. 8.4.15 Small-Signal Model for Frequency Compensation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Switching Frequency
        2. 9.2.2.2 Output Inductor Selection
        3. 9.2.2.3 Output Capacitor
        4. 9.2.2.4 Input Capacitor
        5. 9.2.2.5 Slow-Start Capacitor
        6. 9.2.2.6 Bootstrap Capacitor Selection
        7. 9.2.2.7 Output Voltage and Feedback Resistor Selection
        8. 9.2.2.8 Compensation
        9. 9.2.2.9 Power-Dissipation Estimate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.8 Compensation

There are several industry techniques used to compensate dc-dc regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS57112C-Q1 device. As a result of ignoring the slope compensation, the actual crossover frequency is usually lower than the crossover frequency used in the calculations. Use SwitcherPro software for a more-accurate design.

To get started, calculate the modulator pole, f(p,mod), and the ESR zero, f(z,mod), using Equation 35 and Equation 36. For C(OUT), derating the capacitor is not needed, as the 1.8-V output is a small percentage of the 10-V capacitor rating. If the output is a high percentage of the capacitor rating, use the manufacturer information for the capacitor to derate the capacitor value. Use Equation 37 and Equation 38 to estimate a starting point for the crossover frequency, f(c). For the example design, f(p,mod) is 6.03 kHz and f(z,mod) is 1210 kHz. Equation 37 is the geometric mean of the modulator pole and the ESR zero, and Equation 38 is the mean of modulator pole and the switching frequency. Equation 37 yields 85.3 kHz and Equation 38 gives 54.9 kHz. Use the lower value of Equation 37 and Equation 38 as the approximate crossover frequency. For this example, f(c) is 56 kHz. Next, calculate the compensation components. Use a resistor in series with a capacitor to create a compensating zero. A capacitor in parallel with these two components forms the compensating pole (if needed).

Equation 35. TPS57112C-Q1 comp_eq1_SLVSAH5.gif
Equation 36. TPS57112C-Q1 comp_eq2_SLVSAH5.gif
Equation 37. TPS57112C-Q1 comp_eq3_SLVSAH5.gif
Equation 38. TPS57112C-Q1 comp_eq4_SLVSAH5.gif

The compensation design takes the following steps:

  1. Set up the anticipated crossover frequency. Use Equation 39 to calculate the resistor value for the compensation network. In this example, the anticipated crossover frequency (f(c)) is 56 kHz. The power-stage gain (gmps) is 14 S, and the error-amplifier gain (gmea) is 245 μS.
    2. Equation 39. TPS57112C-Q1 eq26_r3_SLVSAH5.gif
  2. Place compensation zero at the pole formed by the load resistor and the output capacitor. Calculate the capacitor for the compensation network from Equation 40.
    3. Equation 40. TPS57112C-Q1 eq27_c3_SLVSAH5.gif
  3. An extra pole can be added to attenuate high-frequency noise. In this application, the extra pole is not necessary.

From the procedures above, the compensation network includes a 7.68-kΩ resistor and a 3300-pF capacitor.