7.3.14 How to Interface to RT/CLK Pin

The designer can use the RT/CLK pin to synchronize the regulator to an external system clock. To implement the synchronization feature, connect a square wave to the RT/CLK pin through the circuit network shown in Figure 35. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on-time greater than 40 ns and an off-time greater than 40 ns. The synchronization frequency range is 300 to 2200 kHz. The rising edge of PH synchronizes to the falling edge of the signal on the RT/CLK pin. Design the external synchronization circuit in such a way that the device has the default frequency-set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. TI recommends using a frequency-set resistor connected as shown in Figure 35 through a 50-Ω resistor to ground. The resistor should set the switching frequency close to the external CLK frequency. TI recommends ac-coupling the synchronization signal through a 10-pF ceramic capacitor and a 4-kΩ series resistor to the RT/CLK pin. The series resistor reduces PH jitter in heavy-load applications when synchronizing to an external clock, and in applications which transition from synchronizing to RT mode. The first time CLK rises above the CLK threshold, the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage source opens and the CLK pin becomes high-impedance as the PLL starts to lock onto the external signal. Because there is a PLL on the regulator, the switching frequency can be higher or lower than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then increases or decreases the switching frequency until the PLL locks onto the CLK frequency within 100 µs.

When the device transitions from the PLL to resistor mode, the switching frequency slows down from the CLK frequency to 150 kHz; then reapply the 0.5-V voltage, and the resistor then sets the switching frequency. The divisor of the switching frequency goes to 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on the VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal start-up and fault conditions. Figure 36, Figure 37, and Figure 38 show the device synchronized to an external system clock in continuous-conduction mode (CCM), discontinuous-conduction mode (DCM), and pulse-skip mode (PSM).

Figure 35. Synchronizing to a System Clock

Figure 36. Plot of Synchronizing in CCM

Figure 38. Plot of Synchronizing in PSM

Figure 37. Plot of Synchronizing in DCM