SLVSD01B September 2015 – May 2019 TPS57140-EP
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
BOOT | 1 | O | The device requires a bootstrap capacitor between BOOT and PH. A voltage on this capacitor below the minimum required by the output device forces the output to switch off pending a refresh of the capacitor. | |
COMP | 8 | O | Error-amplifier output and input to the output-switch current comparator. Connect frequency-compensation components to this pin. | |
EN | 3 | I | Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input UVLO with two resistors. | |
GND | 9 | — | Ground | |
PH | 10 | I | The source of the internal high-side power MOSFET | |
PWRGD | 6 | O | An open-drain output, asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or EN shutdown. | |
RT/CLK | 5 | I | Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. Pulling the pin above the PLL upper threshold causes a mode change whereby the pin becomes a synchronization input. Disabling of the internal amplifier occurs, and the pin is a high-impedance clock input to the internal PLL. If clocking edges stop, re-enabling of the internal amplifier occurs, and the mode returns to a resistor-set function. | |
SS/TR | 4 | I | Slow-start and tracking. An external capacitor connected to this pin sets the output rise time. The voltage on this pin overrides the internal reference, allowing use of the pin for tracking and sequencing. | |
VIN | 2 | I | Input supply voltage, 3.5 to 42 V | |
VSENSE | 7 | I | Inverting node of the transconductance (gm) error amplifier | |
Thermal pad | — | — | GND pin must have an electrical connection to the exposed pad on the printed-circuit board for proper operation. |