SLVS302B December   2000  – October 2015 TPS60300 , TPS60301 , TPS60302 , TPS60303

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-Good Detector
    4. 9.4 Device Functional Modes
      1. 9.4.1 Start-up Procedure
      2. 9.4.2 Shutdown
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Capacitor Selection
        2. 10.2.2.2 Output Filter Design
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Power Dissipation
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12 Layout

12.1 Layout Guidelines

All capacitors must be soldered as close as possible to the IC. A PCB layout proposal for a two-layer board is shown in Figure 24. Care has been taken to connect all capacitors as close as possible to the circuit to achieve optimized output voltage ripple performance. The bottom layer is not shown in Figure 24. It only consists of a ground-plane with a single track between the two vias that can be seen in the left part of the top layer.

12.2 Layout Example

TPS60300 TPS60301 TPS60302 TPS60303 layoutex1.png Figure 24. Recommended PCB Layout for TPS6030x (Top Layer)

12.3 Power Dissipation

The thermal resistance of the unsoldered package is RθJA = 294°C/W. Soldered on the EVM, a typical thermal resistance of RθJA(EVM) = 200°C/W was measured.

The thermal resistance can be calculated as shown in Equation 4.

Equation 4. TPS60300 TPS60301 TPS60302 TPS60303 Eq04_Rtheta_slvs302.gif

where

  • TJ is the junction temperature.
  • TA is the ambient temperature.
  • PD is the power that needs to be dissipated by the device.

The maximum power dissipation can be calculated as shown in Equation 5.

Equation 5. PD = VIN × IIN – VOUT × IOUT = VIN(max) × [(3 × IOUT + I(SUPPLY)] – VOUT × IOUT

The maximum power dissipation happens with maximum input voltage and maximum output current:

At maximum load the supply current is approximately 2 mA.

Equation 6. PD = 1.8 V × (3 × 20 mA + 2 mA) – 3.3 V × 20 mA = 46 mW.

With this maximum rating and the thermal resistance of the device on the EVM, the maximum temperature rise above ambient temperature can be calculated as shown in Equation 7.

Equation 7. ΔTJ = RθJA × PD = 200°C/W × 46 mW = 10°C

This means that internal dissipation increases TJ by 10°C.

The junction temperature of the device must not exceed 125°C.

This means the IC can easily be used at ambient temperatures as seen in Equation 8.

Equation 8. TA = TJ(max) – ΔTJ = 125°C – 10°C = 115°C