SLVSCO6 January   2015 TPS61093-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Shutdown And Load Discharge
      2. 8.3.2 Over Load And Over Voltage Protection
      3. 8.3.3 Under Voltage Lockout (UVLO)
      4. 8.3.4 Thermal Shutdown
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 15V Output Boost Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Program
          2. 9.2.1.2.2 Without Isolation FET
          3. 9.2.1.2.3 Start Up
          4. 9.2.1.2.4 Switch Duty Cycle
          5. 9.2.1.2.5 Inductor Selection
          6. 9.2.1.2.6 Input And Output Capacitor Selection
          7. 9.2.1.2.7 Small Signal Stability
        3. 9.2.1.3 Application Curves
      2. 9.2.2 10 V, -10 V Dual Output Boost Converter
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

As for all switching power supplies, especially those running at high switching frequency and high currents, layout is an important design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems. To maximize efficiency, switch rise and fall times are very fast. To prevent radiation of high frequency noise (e.g., EMI), proper layout of the high frequency switching path is essential. Minimize the length and area of all traces connected to the SW pin and always use a ground plane under the switching regulator to minimize interplane coupling. The high current path including the switch and output capacitor contains nanosecond rise and fall times and should be kept as short as possible. The input capacitor needs not only to be close to the VIN pin, but also to the GND pin in order to reduce input supply ripple.

11.2 Layout Example

TPS61093-Q1 layout_lvs992.gif

11.3 Thermal Considerations

The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation of the TPS61093-Q1. Calculate the maximum allowable dissipation, PD(max), and keep the actual dissipation less than or equal to PD(max). The maximum-power-dissipation limit is determined using the following equation:

Equation 10. TPS61093-Q1 eq_pd_lvs892.gif

where

  • TA is the maximum ambient temperature for the application
  • RθJA is the thermal resistance junction-toambient given in Power Dissipation Table

The TPS61093-Q1 comes in a thermally enhanced SON package. This package includes a thermal pad that improves the thermal capabilities of the package. The RθJA of the SON package greatly depends on the PCB layout and thermal pad connection. The thermal pad must be soldered to the analog ground on the PCB. Using thermal vias underneath the thermal pad.