JAJSL22F June   2015  – September 2021 TPS61098 , TPS610981 , TPS610982 , TPS610985 , TPS610986 , TPS610987

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Boost Controller Operation
      2. 8.3.2 Pass-Through Operation
      3. 8.3.3 LDO / Load Switch Operation
      4. 8.3.4 Start Up and Power Down
      5. 8.3.5 Over Load Protection
      6. 8.3.6 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation Modes by MODE Pin
        1. 8.4.1.1 Active Mode
        2. 8.4.1.2 Low Power Mode
      2. 8.4.2 Burst Mode Operation under Light Load Condition
      3. 8.4.3 Pass-Through Mode Operation
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 VMAIN to Power MCU and VSUB to Power Subsystem
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Device Choice
          2. 9.2.1.2.2 Maximum Output Current
          3. 9.2.1.2.3 Inductor Selection
          4. 9.2.1.2.4 Capacitor Selection
          5. 9.2.1.2.5 Control Sequence
        3. 9.2.1.3 Application Curves
      2. 9.2.2 VMAIN to Power the System in Low Power Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 VSUB to Power the System in Active Mode
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.3 LDO / Load Switch Operation

The TPS61098x uses a PMOS as a pass element of its integrated LDO / load switch. The input of the PMOS is connected to the output of the boost converter. When the MODE pin is pulled logic high, the PMOS is enabled to output a voltage on VSUB pin.

For load switch version, the PMOS pass element is fully turned on when enabled, no matter the boost converter works in boost operation mode or pass-through operation mode. So the output voltage at VSUB pin is decided by the output voltage at VMAIN pin and the current passing through the PMOS as Equation 2:

Equation 2. GUID-5A4B438F-2536-4692-8B3F-452CE4A58AD2-low.gif

where

  • I(SUB) is the load of VSUB rail
  • RLS is the resistance of the PMOS when it is fully turned on

For LDO version, the output voltage V(SUB) is regulated at the set value when the voltage difference between its input and output is higher than the dropout voltage V(Dropout), no matter the boost converter works in boost operation mode or pass-through operation mode. The V(SUB) is monitored via an internal feedback network which is connected to the voltage error amplifier. To regulate V(SUB), the voltage error amplifier compares the feedback voltage to the internal voltage reference and adjusts the gate voltage of the PMOS accordingly. When the voltage drop across the PMOS is lower than the dropout voltage, the PMOS will be fully turned on and the output voltage at V(SUB) is decided by Equation 2.

When the MODE pin is pulled low, the LDO or load switch is turned off to disconnect the load at VSUB pin. For some versions, active discharge function at VSUB pin is offered, which can discharge the V(SUB) to ground after MODE pin is pulled low, to avoid any bias condition to downstream devices. For versions without the active discharge function, the VSUB pin is floating after MODE pin is pulled low, and its voltage normally drops down slowly due to leakage. Refer to the Section 5 for version differences.

When MODE pin is toggled from low to high, soft-start is implemented for the LDO versions to avoid inrush current during LDO startup. The start up time of LDO is typically 1 ms. For load switch versions, the load switch is turned on faster, so the output capacitor at VSUB pin is suggested 10X smaller than the output capacitor at VMAIN pin to avoid obvious voltage drop of V(MAIN) during load switch turning on process.