SLVS427D JUNE   2002  – May 2015 TPS61120 , TPS61121 , TPS61122

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Controller Circuit
      2. 9.3.2 Synchronous Rectifier
      3. 9.3.3 LDO
      4. 9.3.4 Device Enable
        1. 9.3.4.1 Undervoltage Lockout
        2. 9.3.4.2 Softstart
      5. 9.3.5 LDO Enable
      6. 9.3.6 Power Good
      7. 9.3.7 Low Battery Detector Circuit—LBI/LBO
      8. 9.3.8 Low-EMI Switch
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Save Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Solution for Maximum Output Power
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Programming the Output Voltage
            1. 10.2.1.2.1.1 DC-DC Converter
            2. 10.2.1.2.1.2 LDO
          2. 10.2.1.2.2 Programming the LBI/LBO Threshold Voltage
          3. 10.2.1.2.3 Inductor Selection
          4. 10.2.1.2.4 Capacitor Selection
            1. 10.2.1.2.4.1 Input Capacitor
            2. 10.2.1.2.4.2 Output Capacitor DC-DC Converter
              1. 10.2.1.2.4.2.1 Small Signal Stability
            3. 10.2.1.2.4.3 Output Capacitor LDO
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Low Profile Solution, Maximum Height 1.8 mm
      3. 10.2.3 Dual Power Supply With Auxiliary Positive Output Voltage
      4. 10.2.4 Dual Power Supply With Auxiliary Negative Output Voltage
      5. 10.2.5 Single Output Using LDO as Filter
      6. 10.2.6 Dual Input Power Supply Solution
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|16
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

PW Package
16-Pin TSSOP
Top View
TPS61120 TPS61121 TPS61122 PO_LVS427.gif
RSA Package
16-Pin VQFN With Thermal Pad
Top View
TPS61120 TPS61121 TPS61122 PO1_LVS427.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
TSSOP VQFN
EN 7 5 I DC-DC-enable input. (1: VBAT enabled, 0: GND disabled)
FB 15 13 I DC-DC voltage feedback of adjustable versions
GND 12 10 I/O Control/logic ground
LBI 5 3 I Low battery comparator input (comparator enabled with EN)
LBO 13 11 O Low battery comparator output (open drain)
LDOEN 8 6 I LDO-enable input (1: LDOIN enabled, 0: GND disabled)
LDOOUT 10 8 O LDO output
LDOIN 9 7 I LDO input
LDOSENSE 11 9 I LDO feedback for voltage adjustment, must be connected to LDOOUT at fixed output voltage versions
SWP 1 15 I DC-DC rectifying switch input
PGND 3 1 I/O Power ground
PGOOD 14 12 O DC-DC output power good (1: good, 0 : failure) (open drain)
SKIPEN 6 4 I Enable/disable power save mode (1: VBAT enabled, 0: GND disabled)
SWN 2 16 I DC-DC switch input
VBAT 4 2 I Supply pin
VOUT 16 14 O DC-DC output