10.1 Layout Guidelines

As for all switching power supplies, especially those providing high current and using high switching frequencies, layout is an important design step. If layout is not carefully done, the regulator could show instability as well as EMI problems. Therefore, use wide and short traces for high current paths. The VDD capacitor, C3 (see Figure 23) is the filter and noise decoupling capacitor for the internal linear regulator powering the internal digital circuits. It should be placed as close as possible between the VDD and PGND pins to prevent any noise insertion to digital circuits. The switch node at the drain of Q1 carries high current with fast rising and falling edges. Therefore, the connection between this node to the inductor and the schottky diode should be kept as short and wide as possible. It is also beneficial to have the ground of the capacitor C3 close to the ground of the current sense resistor R7 since there is large driving current flowing between them. The ground of output capacitor EC2 should be kept close to input power ground or through a large ground plane because of the large ripple current returning to the input ground. When laying out signal grounds, it is recommended to use short traces separate from power ground traces and connect them together at a single point, for example on the thermal pad in the PWP package. Resistors R3, R4, R9, R10, R11, and R12 (see Figure 23) are setting resistors for switching frequency, LED current, protection threshold and feedback voltage programming. To avoid unexpected noise coupling into the pins and affecting the accuracy, these resistors need to be close to the pins with short and wide traces to GND. In the PWP package, the thermal pad needs to be soldered to the large ground plane on the PCB for better thermal performance. Additional thermal via can significantly improve power dissipation of the device.

10.2 Layout Example

Figure 26. Layout Example