9.3.1.1 Dedicated LED Privacy Indicator

The TPS6131x device provides a high-side linear constant current source to drive low V_F LEDs. The LED current is directly regulated off the battery and can be controlled through the INDC[3:0] bits, from 2.6 mA to 15.8 mA in 7 programable current steps.

The device can drive two possible hardware configurations shown in Figure 28 and Figure 29. In Figure 28 the TPS6131x device drives a privacy indicator LED towards ground.

Figure 28. Configuration 1

Figure 29. Configuration 2

The TPS6131x device also allows a path for driving a privacy indicator LED that is reverse biased to the white flash LED, see Figure 29. To do so, the output of the converter (VOUT) is pulled to ground thus allowing a reverse current to flow. This mode of operation is only possible when the converter’s power stage is in shutdown (MODE_CTRL[1:0] = 00, ENVM = 0).

9.3.1.2 White LED Privacy Indicator

The TPS6131x device features white LED drive capability at very low light intensity. To generate a reduced LED average current, the device employs a 30-kHz fixed-frequency PWM modulation scheme. The PWM timer uses the internal oscillator as reference clock, therefore the PWM modulating frequency shows the same accuracy as the internal reference clock. Operation is shown in Figure 27.

The video light current is modulated with a duty cycle defined by the INDC[3:0] bits. The low light dimming mode can only be activated in the software-controlled video-light-only mode (MODE_CTRL[1:0] = 01, ENVM = 1), and applies to the LEDs selected through ENLED[3:1] bits. In this mode, the video light safety-timeout feature is disabled.

Figure 30. PWM Dimming Principle

9.3.2.1 LED Temperature Monitoring (Finger-Burn Protection)

The TPS6131x device optionally monitors the LED temperature. Critical temperatures are handled in two stages reflected by two bits: LEDWARN provides an early warning to the camera engine, LEDHOT immediately suspends the flash operation.

The LED temperature is sensed by measuring the voltage drop of a negative-temperature-coefficient resistor connected between the TS and AGND pins. An internal current source provides the bias (approximately 24 µA) for the NTC, and the TS pin voltage is compared to internal thresholds (1.05 V and 0.345 V) to protect the LEDs against overheating. See NTC Selection.

The temperature-monitoring blocks are explicitly active in video light or flash modes. In voltage-mode operation [MODE_CTRL[1:0] = 11], the device only activates the TS input when the ENTS bit is set high.

The LEDWARN and LEDHOT bits reflect the LED temperature. The LEDWARN bit is set when the voltage at the TS pin is lower than 1.05 V. This threshold corresponds to an LED warning temperature value; device operation is still permitted. While regulating LED current, video light or flash modes, the LEDHOT bit is latched when the voltage at the TS pin is lower than 0.345 V. This threshold corresponds to an excessive LED temperature value; device operation is immediately suspended, (MODE_CTRL[1:0] bits are reset, and the HOTDIE[1:0] bits are set).

9.3.2.2 LED Failure Modes (Open and Short Detection) and Overvoltage Protection

The TPS6131x devices incorporate protection features to indicate if the connected LEDs are failing. These protections cover overvoltage conditions, which are caused by a failing LED showing open circuit behavior, as well as short-circuit conditions caused by a failing LED or further reasons causing a short-circuit condition. If such failure conditions occur, these are indicated by setting a failure detection flag. Furthermore, the maximum current drawn from the output is limited and can be programmed by the current-limit setting.

9.3.2.3 LED Current Ramp-Up and Ramp-Down

To achieve smooth LED current waveforms and avoid excessive battery voltage drop, the TPS6131x device actively controls the LED current ramp-up and ramp-down sequence.

Figure 31. LED Current Slew Rate Control

9.3.2.4 Battery Voltage Droop Monitoring and Protection

During a high-power flash strobe, the battery voltage usually drops by a few hundred millivolts. To prevent the battery voltage from collapsing too much, the TPS6131x devices integrates a battery voltage droop monitoring feature to automatically limit the flash current if the battery voltage drops more than a programmable threshold.

The battery voltage droop monitoring feature can be enabled or disabled through the ENBATMON bit.

At the very beginning of the flash strobe, the device measures the battery voltage and sets a minimum battery voltage threshold based on the tolerable droop (see REGISTER7 (address = 0x07) for BATDROOP[2:0] bits). While the LED current is increasing to the target flash current (see REGISTER1 (address = 0x01) and REGISTER2 (address = 0x02) for FC13[4:0] and FC2[5:0] bits), a comparator monitors the actual battery voltage and stops the ramp-up sequence when the droop exceeds the limit. See Functional Block Diagram and Figure 32.

The battery voltage droop monitor feature is automatically disabled during a Tx-MASK event.

Figure 32. Battery Voltage Droop Monitoring and LED Current Control Principle (STRB1 = 0, Tx-Base = 1)

9.3.2.5 Undervoltage Lockout

The undervoltage lockout circuit prevents the device from error conditions at low input voltages. It prevents the converter from turning on the switch MOSFET, or rectifier MOSFET for battery voltages below 2.3 V. The I²C compatible interface is fully functional down to 2.1-V input voltage.

9.3.2.6 Hot Die Detection and Thermal Shutdown

The TPS6131x device offers two levels of die temperature monitoring and protection, which are hot die detection and thermal shutdown functionality. The hot die detector (HOTDIE[1:0] bits) reflects the instantaneous junction temperature. This functionality is always enabled except when the device is in shutdown mode.

The hot die detector monitors the junction temperature but does not shut down the device. It provides an early warning to the camera engine to avoid excessive power dissipation thus preventing from thermal shutdown during the next high-power flash strobe.

As soon as the junction temperature T_J exceeds 160°C typical, the device goes into thermal shutdown. In this mode, the power stage and the low-side current regulators are turned off, the HOTDIE[1:0] bits are set and can only be reset by a read access. In the voltage mode operation (MODE_CTRL[1:0] = 11 or ENVM = 1), the device continues its operation when the junction temperature falls below 140°C typical again. In the current regulation mode, video light or flash modes, device operation is suspended.

9.3.2.7 Current Limit

The TPS6131x devices employ a programmable inductor current limit. This allows choosing inductors with different saturation current ratings. Furthermore, this provides protection against a shorted inductor, or if the inductance value dramatically drops. This protects the battery from excessively high current drain.

The current limit circuit employs a valley current sensing scheme. The detection threshold is user selectable through the ILIM bit. The ILIM bit can only be set before entering operation, during initial shutdown state.

Figure 33 illustrates the inductor and rectifier current waveforms during current limit operation. The output current, IOUT, is the average of the rectifier ripple current waveform. When the load current is increased such that the lower peak is above the current limit threshold, the off time is lengthened to allow the current to decrease to this threshold before the next ON time begins (so called frequency foldback mechanism).

Both the output voltage and the switching frequency are reduced as the power stage of the device operates in a constant current mode. The maximum continuous output current (I_OUT(CL)), before entering current limit operation, can be defined as:

Equation 1.

The TPS6131x device also provides a negative current limit (≈ 300 mA) to prevent an excessive reverse inductor current when the power stage sinks current from the output in the forced continuous conduction mode.

Table 5. Inductor Current Limit Operation

9.3.2.8 Flash Blanking (Tx-Mask) for Instantaneous Flash Current Reduction

The TPS6131x devices offer a dedicated hardware signal input (Tx-Mask) that can be used to reduce the flash current to the programmed video light level instantaneously.

This feature can be used to reduce the overall current drawn from the battery if other system components require high energy simultaneously, such as during a RF PA transmission pulse.

The Tx-MASK function has no influence on the safety timer duration.

Figure 34. Synchronized Flash With Blanking Periods (STRB1 = 0)

9.3.5.1 F/S-Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 35. All I²C-compatible devices must recognize a start condition.

Figure 35. Start and Stop Conditions

The master then generates the SCL pulses, and transmits the 7-bit address and the read or write direction bit (R/W) on the SDA line. During all transmissions, the master checks for valid data. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 36). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 37) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established.

Figure 36. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver must to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 35). This releases the bus and stops the communication link with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address.

Attempting to read data from register addresses not listed in this section results in 00h being read out.

Figure 37. Acknowledge on the I²C Bus

Figure 38. Bus Protocol

9.3.5.2 H/S-Mode Protocol

The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the H/S-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in H/S-mode.

Attempting to read data from register addresses not listed in this section results in 00h being read out.

9.3.5.3 TPS6131x I²C Update Sequence

The TPS6131x requires a start condition, a valid I²C address, a register address byte, and a data byte for a single update. After the receipt of each byte, TPS6131x device acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I²C address selects the TPS6131x. TPS6131x performs an update on the falling edge of the acknowledge signal that follows the LSB byte.

Figure 39. : Write Data Transfer Format in F/S-Mode

Figure 40. Read Data Transfer Format in F/S-Mode

Figure 41. Data Transfer Format in H/S-Mode

9.3.5.4 Slave Address Byte

The slave address byte is the first byte received following the START condition from the master device.

9.3.5.5 Register Address Byte

Following the successful acknowledgment of the slave address, the bus master sends a byte to the TPS6131x, which contains the address of the register to be accessed.

9.4.1.1 LED Hardware Setup

The TPS6131x device uses LED forward-voltage sensing circuitry on LED1, LED2, and LED3 pins to optimize the power-stage boost ratio for maximum efficiency. Due to the nature of the sensing circuitry, TI does not recommend leaving any of the LED1, LED2, and LED3 pins unused if the operation is selected through ENLED[3:1] bits. Leaving LED1, LED2, and LED3 pins unconnected, while the respective ENLEDx bits have been set, forces the control loop into high gain, and eventually trips the output overvoltage protection. Figure 43 shows the recommended LED setup for a single, dual or triple-LED application.

Figure 43. White LED Hardware Setup Options

The LED1, LED2, and LED3 inputs may be connected together to drive one or two LEDs at higher currents. Connecting the current sink inputs in parallel does not affect the internal operation of the TPS6131x. For best operation, TI recommends disabling the LED inputs that are not connected. (see the ENLED[3:1] bits description in REGISTER5 (address = 0x05)).

The video light currents are individually programmed through the video light control bits DCL13[2:0] and DCL2[2:0] , the flash currents through FC2[5:0] and FC13[4:0] bits accordingly. If, for single or dual LED application as shown in Figure 43, current sinks are connected to each other and enabled, the resulting video or flash current is the sum of the programmed currents.

9.4.1.2 Triggering Video Light and Flash

For most flexible system integration, the TPS6131x offers several options for activating the video light and flash. Depending on the settings of the MODE_CTRL[1:0] bits, the device can enter different modes of operation. It offers the option of triggering the video light and flash through hardware signals (STRB0, STRB1) or software I²C command. The flash-signal hardware trigger can be on the leading-edge, turning on for the programmed flash on time, or level sensitive, turning on for as long as the signal is logic high.

The TPS6131x flash timer is programmed through the STIM[2:0] and SELSTIM bits. If the flash is fired by a rising-edge trigger or by an I²C command, the timer defines the flash duration. If the flash is fired by a level-sensitive trigger, the timer defines the maximum flash ON duration, and overrides the hardware signal if the programmed on-time is exceeded.

For video lighting, a watchdog timer is implemented; this must be refreshed within 13 seconds. This function can be disabled, as described in Table 6.

The dual-wire camera-module interface STRB0 and STRB1 inputs are used for selecting the video light (STRB1 = 1) or flash (STRB1 = 0) mode. The STRB0 signal then triggers the video light or flash, depending on the state of STRB1. The STT bit defines if the flash trigger is level sensitive (STT = 0), or fired on the rising edge (STT = 1).

9.4.1.3 Level-Sensitive Flash Trigger (STT = 0)

In this mode, the high-power LEDs are driven at the flash current level and the safety timer (STIM) is running. The maximum duration of the flash pulse is defined in the STIM[2:0] register.

The safety timer is triggered on rising edge and stopped by a negative logic on the synchronization source (STRB0, STRB1 = 0) or by a timeout event (TO bit).

Figure 44. Hardware Synchronized Video Light and Flash Strobe

9.4.1.4 Rising-Edge Flash Trigger (STT = 1)

In this mode, the high-power LEDs are driven at the flash current level and the safety timer (STIM) is running. The duration of the flash pulse is defined in the STIM[2:0] register.

The flash strobe is started either by a rising edge on the synchronization source (STRB0 = 1, STRB1 = 0) or by a positive transition on the START-FLASH/TIMER (SFT) bit (STRB0 = 1, STRB1 = 0). Once running, the timer ignores all kind of triggering signals and only stops after a timeout (TO). START-FLASH/TIMER (SFT) bit is being reset by the timeout (TO) signal.

Figure 45. Edge Sensitive Timer (Single Trigger Event)

Table 7. Voltage Mode Description

9.4.2.1 Down Mode in Voltage Mode Operation

In general, a boost converter only regulates output voltages which are higher than the input voltage. The TPS6131x can regulate 4.2 V at the output with an input voltage as high as 5.5 V. To control these applications properly, a down-conversion mode is implemented.

In voltage-regulation mode, if the input voltage reaches or exceeds the output voltage, the converter changes to down-conversion mode. In this mode, the control circuit changes the behavior of the rectifying PMOS. It sets the voltage drop across the PMOS as high as required to regulate the output voltage. This increases the power losses in the converter, and must be considered for thermal design. The down-conversion mode is automatically turned off as soon as the input voltage falls to approximately 200 mV below the output voltage.

For proper operation in down-conversion mode the output voltage must not be programmed higher than approximately 5.3 V. Take care not to violate the absolute maximum ratings at the SW pins.

9.4.2.2 Power Good Indication

The TPS6131x integrates a Power Good circuit that is activated when the device operates in voltage-regulation mode (MODE_CTRL[1:0] = 11 or ENVM = 1). In shutdown mode (MODE_CTRL[1:0] = 00, ENVM = 0), the GPIO/PG pin state is defined below, according to the GPIOTYPE bit:

Depending on the GPIO/PG output stage type selection, push-pull or open-drain, the polarity of the Power Good output signal (PG) can be inverted or not. The Power Good software bit and hardware signal polarity is defined below:

The Power Good signal is true when the output voltage is from –1.5% to 2.5% of its nominal value. Conversely, it is false when the voltage-mode operation is suspended (MODE_CTRL[1:0] ≠ 11 and ENVM = 0).

Figure 46. Power Good Operation (DIR = 1, GPIOTYPE = 1)

The TPS6131x device uses a control architecture that recycles excess energy that might be stored in the output capacitor. By reversing the operation of the boost power stage, the converter is capable of transferring energy from its output back into the input source. In this case, the Power Good signal is deasserted while the output voltage is decreasing towards its target value, the closest fit voltage the converter can support.

Table 10. REGISTER0 Field Descriptions

Table 11. REGISTER1 Field Descriptions

Table 12. REGISTER2 Field Descriptions

Table 13. REGISTER3 Field Descriptions

Table 14. REGISTER4 Field Descriptions

Table 15. REGISTER5 Field Descriptions

Table 16. REGISTER6 Field Descriptions

Table 17. REGISTER7 Field Descriptions