JAJSLN3B March   2021  – October 2021 TPS61379-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  VCC Power Supply
      2. 8.3.2  Input Undervoltage Lockout (UVLO)
      3. 8.3.3  Enable and Soft Start
      4. 8.3.4  Shut Down
      5. 8.3.5  Switching Frequency Setting
      6. 8.3.6  Spread Spectrum Frequency Modulation
      7. 8.3.7  Bootstrap
      8. 8.3.8  Load Disconnect
      9. 8.3.9  MODE/SYNC Configuration
      10. 8.3.10 Overvoltage Protection (OVP)
      11. 8.3.11 Output Short Protection/Hiccup
      12. 8.3.12 Power-Good Indicator
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced PWM Mode
      2. 8.4.2 Auto PFM Mode
      3. 8.4.3 External Clock Synchronization
      4. 8.4.4 Down Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Output Voltage
        2. 9.2.2.2 Setting the Switching Frequency
        3. 9.2.2.3 Selecting the Inductor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Input Capacitors
        6. 9.2.2.6 Loop Stability and Compensation
          1. 9.2.2.6.1 Small Signal Model
          2. 9.2.2.6.2 Loop Compensation Design Steps
          3. 9.2.2.6.3 Selecting the Bootstrap Capacitor
          4. 9.2.2.6.4 VCC Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 用語集
    6. 12.6 静電気放電に関する注意事項
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-20210107-CA0I-Z3F0-CNKZ-S5RLZ0KD9974-low.gif Figure 6-1 16-Pin WQFN RTE Package (Transparent Top View)
Table 6-1 Pin Functions
PINI/ODESCRIPTION
NAMENO.
VIN1IIC power supply input
BST2IPower supply for high-side N-MOSFET gate drivers. A capacitor must be connected between this pin and SW pin.
SW3, 4PWRThe switching node pin of the converter. It is connected to the drain of the internal low-side FET and the source of the high-side FET.
MODE/SYNC5IMode selection pin. MODE = high, forced PWM mode. MODE = low or floating, auto PFM mode. This pin can also be used to synchronize the external clock. Refer to Table 8-1 for details.
VCC6OOutput of internal regulator. A ceramic capacitor with more than 1 μF must be connected between this pin and GND.
GND7, 8PWRPower ground of the IC. It is connected to the source of the low-side FET.
VO9PWROutput of the isolation FET. Connect load to this pin to achieve input/output isolation.
OUT10PWROutput of the drain of the HS FET. Connect this pin as the output can disable the load disconnect/short protection feature (or short this pin with VO pin).
PG11OPower good indicator, open-drain output
NC12INo connection pin
FB13IFeedback pin. Use a resistor divider to set the desired output voltage. Refer to Section 9.2.2.1 for details.
COMP14IOutput of the internal transconductance error amplifier. An external RC network is connected to this pin to optimize the loop stability and response time.
EN15IEnable logic input
FREQ16IFrequency setting pin. Connect a resistor between this pin and GND pin to set the desired frequency.
Thermal Pad--The thermal pad must be connected to power ground plane for good power dissipation.