JAJSLN3B March   2021  – October 2021 TPS61379-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  VCC Power Supply
      2. 8.3.2  Input Undervoltage Lockout (UVLO)
      3. 8.3.3  Enable and Soft Start
      4. 8.3.4  Shut Down
      5. 8.3.5  Switching Frequency Setting
      6. 8.3.6  Spread Spectrum Frequency Modulation
      7. 8.3.7  Bootstrap
      8. 8.3.8  Load Disconnect
      9. 8.3.9  MODE/SYNC Configuration
      10. 8.3.10 Overvoltage Protection (OVP)
      11. 8.3.11 Output Short Protection/Hiccup
      12. 8.3.12 Power-Good Indicator
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced PWM Mode
      2. 8.4.2 Auto PFM Mode
      3. 8.4.3 External Clock Synchronization
      4. 8.4.4 Down Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Output Voltage
        2. 9.2.2.2 Setting the Switching Frequency
        3. 9.2.2.3 Selecting the Inductor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Input Capacitors
        6. 9.2.2.6 Loop Stability and Compensation
          1. 9.2.2.6.1 Small Signal Model
          2. 9.2.2.6.2 Loop Compensation Design Steps
          3. 9.2.2.6.3 Selecting the Bootstrap Capacitor
          4. 9.2.2.6.4 VCC Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 用語集
    6. 12.6 静電気放電に関する注意事項
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.5 Selecting the Input Capacitors

Multilayer ceramic capacitors are an excellent choice for the input decoupling of the step-up converter as they have extremely low ESR and are available in small footprints. Input capacitors must be located as close as possible to the device. While a 22-µF input capacitor or equivalent is sufficient for the most applications, larger values can be used to reduce input current ripple.

Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part. Additional "bulk" capacitance (electrolytic or tantalum) in this circumstance, must be placed between CIN and the power source lead to reduce ringing that can occur between the inductance of the power source leads and CIN.